JPS60115093A - メモリセル及びアレイ - Google Patents

メモリセル及びアレイ

Info

Publication number
JPS60115093A
JPS60115093A JP59236003A JP23600384A JPS60115093A JP S60115093 A JPS60115093 A JP S60115093A JP 59236003 A JP59236003 A JP 59236003A JP 23600384 A JP23600384 A JP 23600384A JP S60115093 A JPS60115093 A JP S60115093A
Authority
JP
Japan
Prior art keywords
transistor
emitter
array
transistors
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59236003A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0430678B2 (https=
Inventor
バリー　エイ．ホバーマン
ウイリアム　イー．モス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MONORISHITSUKU MEMORY ZU Inc
MONORISHITSUKU MEMORY-ZU Inc
Original Assignee
MONORISHITSUKU MEMORY ZU Inc
MONORISHITSUKU MEMORY-ZU Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MONORISHITSUKU MEMORY ZU Inc, MONORISHITSUKU MEMORY-ZU Inc filed Critical MONORISHITSUKU MEMORY ZU Inc
Publication of JPS60115093A publication Critical patent/JPS60115093A/ja
Publication of JPH0430678B2 publication Critical patent/JPH0430678B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
JP59236003A 1983-11-10 1984-11-10 メモリセル及びアレイ Granted JPS60115093A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/551,736 US4574367A (en) 1983-11-10 1983-11-10 Memory cell and array
US551736 1983-11-10

Publications (2)

Publication Number Publication Date
JPS60115093A true JPS60115093A (ja) 1985-06-21
JPH0430678B2 JPH0430678B2 (https=) 1992-05-22

Family

ID=24202465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59236003A Granted JPS60115093A (ja) 1983-11-10 1984-11-10 メモリセル及びアレイ

Country Status (4)

Country Link
US (1) US4574367A (https=)
EP (1) EP0142266B1 (https=)
JP (1) JPS60115093A (https=)
DE (2) DE3486261T2 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922411A (en) * 1988-12-27 1990-05-01 Atmel Corporation Memory cell circuit with supplemental current

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3487376A (en) * 1965-12-29 1969-12-30 Honeywell Inc Plural emitter semiconductive storage device
US3764825A (en) 1972-01-10 1973-10-09 R Stewart Active element memory
SU752490A1 (ru) * 1976-06-03 1980-07-30 Предприятие П/Я В-8466 Трехтактный регистр сдвига
US4151609A (en) * 1977-10-11 1979-04-24 Monolithic Memories, Inc. First in first out (FIFO) memory
JPS5564685A (en) * 1978-11-07 1980-05-15 Fujitsu Ltd Semiconductor memory unit

Also Published As

Publication number Publication date
DE142266T1 (de) 1986-03-20
DE3486261T2 (de) 1994-04-28
US4574367A (en) 1986-03-04
EP0142266B1 (en) 1993-12-29
EP0142266A2 (en) 1985-05-22
DE3486261D1 (de) 1994-02-10
EP0142266A3 (en) 1987-07-01
JPH0430678B2 (https=) 1992-05-22

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