DE3480504D1 - Dynamic semiconductor memory having sensing amplifiers - Google Patents

Dynamic semiconductor memory having sensing amplifiers

Info

Publication number
DE3480504D1
DE3480504D1 DE8484103905T DE3480504T DE3480504D1 DE 3480504 D1 DE3480504 D1 DE 3480504D1 DE 8484103905 T DE8484103905 T DE 8484103905T DE 3480504 T DE3480504 T DE 3480504T DE 3480504 D1 DE3480504 D1 DE 3480504D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
dynamic semiconductor
sensing amplifiers
amplifiers
sensing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484103905T
Other languages
English (en)
Inventor
Yukimasa Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3480504D1 publication Critical patent/DE3480504D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
DE8484103905T 1983-06-24 1984-04-09 Dynamic semiconductor memory having sensing amplifiers Expired DE3480504D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58113924A JPH069114B2 (ja) 1983-06-24 1983-06-24 半導体メモリ

Publications (1)

Publication Number Publication Date
DE3480504D1 true DE3480504D1 (en) 1989-12-21

Family

ID=14624598

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484103905T Expired DE3480504D1 (en) 1983-06-24 1984-04-09 Dynamic semiconductor memory having sensing amplifiers

Country Status (4)

Country Link
US (1) US4608666A (de)
EP (1) EP0129651B1 (de)
JP (1) JPH069114B2 (de)
DE (1) DE3480504D1 (de)

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JPS62146491A (ja) * 1985-12-20 1987-06-30 Sanyo Electric Co Ltd 半導体メモリ
DE3786358T2 (de) * 1986-03-10 1993-10-14 Nippon Electric Co Halbleiterspeicher mit System zum seriellen Schnellzugriff.
JPS62245593A (ja) * 1986-04-17 1987-10-26 Sanyo Electric Co Ltd ダイナミツクメモリのデ−タ書き込み方法
JPS62245594A (ja) * 1986-04-17 1987-10-26 Sanyo Electric Co Ltd ダイナミツクメモリのデ−タ書き込み方法
US4979145A (en) * 1986-05-01 1990-12-18 Motorola, Inc. Structure and method for improving high speed data rate in a DRAM
JPS6363196A (ja) * 1986-09-02 1988-03-19 Fujitsu Ltd 半導体記憶装置
US4980863A (en) * 1987-03-31 1990-12-25 Kabushiki Kaisha Toshiba Semiconductor memory device having switching circuit for coupling together two pairs of bit lines
JP2700886B2 (ja) * 1987-11-05 1998-01-21 三菱電機株式会社 半導体集積回路装置
US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor
US5335336A (en) * 1988-03-28 1994-08-02 Hitachi, Ltd. Memory device having refresh mode returning previous page address for resumed page mode
US5724540A (en) * 1988-03-28 1998-03-03 Hitachi, Ltd. Memory system having a column address counter and a page address counter
US4974146A (en) * 1988-05-06 1990-11-27 Science Applications International Corporation Array processor
JP2633645B2 (ja) * 1988-09-13 1997-07-23 株式会社東芝 半導体メモリ装置
EP0372873B1 (de) * 1988-12-05 1997-09-24 Texas Instruments Incorporated Integrierte Schaltungskonfiguration mit schneller örtlicher Zugriffszeit
JPH0316083A (ja) * 1989-03-15 1991-01-24 Matsushita Electron Corp 半導体メモリ装置
DE69023258T2 (de) * 1989-03-15 1996-05-15 Matsushita Electronics Corp Halbleiter-Speichereinrichtung.
CA2011518C (en) * 1989-04-25 1993-04-20 Ronald N. Fortino Distributed cache dram chip and control method
JP2646032B2 (ja) * 1989-10-14 1997-08-25 三菱電機株式会社 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法
JPH0442493A (ja) * 1990-06-07 1992-02-13 Fujitsu Ltd 半導体記憶装置
EP1050820A3 (de) 1990-12-25 2001-06-06 Mitsubishi Denki Kabushiki Kaisha Halbleiterspeichervorrichtung mit einem grossen Speicher und einem Hochgeschwindigkeitsspeicher
JP2829134B2 (ja) * 1990-12-27 1998-11-25 株式会社東芝 半導体記憶装置
JPH07123134B2 (ja) * 1990-12-27 1995-12-25 株式会社東芝 半導体装置
JPH04255989A (ja) 1991-02-07 1992-09-10 Mitsubishi Electric Corp 半導体記憶装置および内部電圧発生方法
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
US5297091A (en) * 1991-10-31 1994-03-22 International Business Machines Corporation Early row address strobe (RAS) precharge
US5377152A (en) * 1991-11-20 1994-12-27 Kabushiki Kaisha Toshiba Semiconductor memory and screening test method thereof
JP2724932B2 (ja) * 1991-12-03 1998-03-09 三菱電機株式会社 デュアルポートメモリ
US5291444A (en) * 1991-12-23 1994-03-01 Texas Instruments Incorporated Combination DRAM and SRAM memory array
EP0895162A3 (de) * 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Verbesserte DRAM mit eingebauten Registern
JP3400824B2 (ja) * 1992-11-06 2003-04-28 三菱電機株式会社 半導体記憶装置
AT397724B (de) * 1992-11-12 1994-06-27 Avl Verbrennungskraft Messtech Dichtungselement
JP3547466B2 (ja) * 1993-11-29 2004-07-28 株式会社東芝 メモリ装置、シリアル‐パラレルデータ変換回路、メモリ装置にデータを書き込む方法、およびシリアル‐パラレルデータ変換方法
US5701270A (en) * 1994-05-09 1997-12-23 Cirrus Logic, Inc. Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same
US5473573A (en) * 1994-05-09 1995-12-05 Cirrus Logic, Inc. Single chip controller-memory device and a memory architecture and methods suitable for implementing the same
US5442588A (en) * 1994-08-16 1995-08-15 Cirrus Logic, Inc. Circuits and methods for refreshing a dual bank memory
US5819305A (en) * 1996-08-23 1998-10-06 Motorola, Inc. Method and apparatus for configuring operating modes in a memory
US6167486A (en) * 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
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JP3161384B2 (ja) 1997-09-16 2001-04-25 日本電気株式会社 半導体記憶装置とそのアクセス方法
JP3092556B2 (ja) * 1997-09-16 2000-09-25 日本電気株式会社 半導体記憶装置
JP3092558B2 (ja) 1997-09-16 2000-09-25 日本電気株式会社 半導体集積回路装置
JP3161383B2 (ja) 1997-09-16 2001-04-25 日本電気株式会社 半導体記憶装置
US5963481A (en) * 1998-06-30 1999-10-05 Enhanced Memory Systems, Inc. Embedded enhanced DRAM, and associated method
KR100318464B1 (ko) * 1998-06-30 2002-02-19 박종섭 재쓰기회로를갖는스태틱램디바이스
JP3178423B2 (ja) 1998-07-03 2001-06-18 日本電気株式会社 バーチャルチャネルｓｄｒａｍ
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JP3307360B2 (ja) 1999-03-10 2002-07-24 日本電気株式会社 半導体集積回路装置
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JP3319421B2 (ja) 1999-03-15 2002-09-03 日本電気株式会社 半導体集積回路装置
US6708254B2 (en) 1999-11-10 2004-03-16 Nec Electronics America, Inc. Parallel access virtual channel memory system
JP3457611B2 (ja) * 2000-02-16 2003-10-20 日本電気株式会社 半導体記憶装置
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US6889290B2 (en) * 2001-06-29 2005-05-03 Intel Corporation Memory management apparatus and method
JP4639030B2 (ja) * 2002-11-18 2011-02-23 パナソニック株式会社 半導体記憶装置
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Also Published As

Publication number Publication date
EP0129651B1 (de) 1989-11-15
JPS607690A (ja) 1985-01-16
JPH069114B2 (ja) 1994-02-02
US4608666A (en) 1986-08-26
EP0129651A3 (en) 1986-12-30
EP0129651A2 (de) 1985-01-02

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Legal Events

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8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)