DE3473971D1 - Method of standardization and stabilization of semiconductor wafers - Google Patents

Method of standardization and stabilization of semiconductor wafers

Info

Publication number
DE3473971D1
DE3473971D1 DE8484430020T DE3473971T DE3473971D1 DE 3473971 D1 DE3473971 D1 DE 3473971D1 DE 8484430020 T DE8484430020 T DE 8484430020T DE 3473971 T DE3473971 T DE 3473971T DE 3473971 D1 DE3473971 D1 DE 3473971D1
Authority
DE
Germany
Prior art keywords
slices
batch
oxygen
determined
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484430020T
Other languages
English (en)
Inventor
Victor Cazcarra
Jocelyne Leroueille
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compagnie IBM France SAS
International Business Machines Corp
Original Assignee
Compagnie IBM France SAS
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie IBM France SAS, International Business Machines Corp filed Critical Compagnie IBM France SAS
Application granted granted Critical
Publication of DE3473971D1 publication Critical patent/DE3473971D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/06—Gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/127—Process induced defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/909—Controlled atmosphere

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE8484430020T 1984-06-20 1984-06-20 Method of standardization and stabilization of semiconductor wafers Expired DE3473971D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP84430020A EP0165364B1 (de) 1984-06-20 1984-06-20 Verfahren zum Standardisieren und Stabilisieren von Halbleiterscheiben

Publications (1)

Publication Number Publication Date
DE3473971D1 true DE3473971D1 (en) 1988-10-13

Family

ID=8192950

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484430020T Expired DE3473971D1 (en) 1984-06-20 1984-06-20 Method of standardization and stabilization of semiconductor wafers

Country Status (3)

Country Link
US (1) US4637123A (de)
EP (1) EP0165364B1 (de)
DE (1) DE3473971D1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6031231A (ja) * 1983-07-29 1985-02-18 Toshiba Corp 半導体基体の製造方法
US4809196A (en) * 1986-04-10 1989-02-28 International Business Machines Corporation Method for designating/sorting semiconductor wafers according to predicted oxygen precipitation behavior
US4868133A (en) * 1988-02-11 1989-09-19 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using RTA
US4851358A (en) * 1988-02-11 1989-07-25 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing
JPH0377329A (ja) * 1989-08-19 1991-04-02 Fujitsu Ltd 半導体装置の製造方法
US5096839A (en) * 1989-09-20 1992-03-17 Kabushiki Kaisha Toshiba Silicon wafer with defined interstitial oxygen concentration
JP3011982B2 (ja) * 1990-09-14 2000-02-21 コマツ電子金属株式会社 半導体装置の製造方法
JPH0750713B2 (ja) * 1990-09-21 1995-05-31 コマツ電子金属株式会社 半導体ウェーハの熱処理方法
EP0502471A3 (en) * 1991-03-05 1995-10-11 Fujitsu Ltd Intrinsic gettering of a silicon substrate
JPH0684925A (ja) * 1992-07-17 1994-03-25 Toshiba Corp 半導体基板およびその処理方法
US5272119A (en) * 1992-09-23 1993-12-21 Memc Electronic Materials, Spa Process for contamination removal and minority carrier lifetime improvement in silicon
KR0139730B1 (ko) * 1993-02-23 1998-06-01 사또오 후미오 반도체 기판 및 그 제조방법
US5494697A (en) * 1993-11-15 1996-02-27 At&T Corp. Process for fabricating a device using an ellipsometric technique
US5611855A (en) * 1995-01-31 1997-03-18 Seh America, Inc. Method for manufacturing a calibration wafer having a microdefect-free layer of a precisely predetermined depth
JP3105770B2 (ja) * 1995-09-29 2000-11-06 日本電気株式会社 半導体装置の製造方法
KR100252214B1 (ko) * 1997-04-23 2000-04-15 윤종용 반도체장치 제조용 베어 웨이퍼 분석방법
US6610550B1 (en) * 2002-04-03 2003-08-26 Advanced Micro Devices Method and apparatus for correlating error model with defect data
US6954711B2 (en) * 2003-05-19 2005-10-11 Applied Materials, Inc. Test substrate reclamation method and apparatus
US7657390B2 (en) * 2005-11-02 2010-02-02 Applied Materials, Inc. Reclaiming substrates having defects and contaminants
FR2974180B1 (fr) 2011-04-15 2013-04-26 Commissariat Energie Atomique Procede de determination de la concentration en oxygene interstitiel.
CN102721697B (zh) * 2012-05-29 2014-04-30 江西赛维Ldk太阳能高科技有限公司 一种晶体硅位错的检测方法及检测系统
FR3133481A1 (fr) * 2022-03-11 2023-09-15 Soitec Procédé de fabrication d’une structure multicouche de type semi-conducteur sur isolant

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583375B2 (ja) * 1979-01-19 1983-01-21 超エル・エス・アイ技術研究組合 シリコン単結晶ウエハ−の製造方法
FR2460479A1 (fr) * 1979-06-29 1981-01-23 Ibm France Procede de caracterisation de la teneur en oxygene des barreaux de silicium tires selon la methode czochralski
EP0042901B1 (de) * 1980-06-26 1984-10-31 International Business Machines Corporation Verfahren zum Kontrollieren des Sauerstoffgehaltes von Siliziumstäben, die nach dem Czochralski-Verfahren hergestellt worden sind
US4342616A (en) * 1981-02-17 1982-08-03 International Business Machines Corporation Technique for predicting oxygen precipitation in semiconductor wafers
US4437922A (en) * 1982-03-26 1984-03-20 International Business Machines Corporation Method for tailoring oxygen precipitate particle density and distribution silicon wafers
JPS58171105A (ja) * 1982-03-31 1983-10-07 Toshiba Corp 振幅変調器

Also Published As

Publication number Publication date
EP0165364A1 (de) 1985-12-27
EP0165364B1 (de) 1988-09-07
US4637123A (en) 1987-01-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee