DE3369428D1 - Process for encapsulating semi-conductor components and encapsulated components so obtained - Google Patents

Process for encapsulating semi-conductor components and encapsulated components so obtained

Info

Publication number
DE3369428D1
DE3369428D1 DE8383103114T DE3369428T DE3369428D1 DE 3369428 D1 DE3369428 D1 DE 3369428D1 DE 8383103114 T DE8383103114 T DE 8383103114T DE 3369428 T DE3369428 T DE 3369428T DE 3369428 D1 DE3369428 D1 DE 3369428D1
Authority
DE
Germany
Prior art keywords
components
encapsulated
conductor
encapsulating
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383103114T
Other languages
English (en)
Inventor
Georges Roche
Jacques Lantaires
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Alcatel Lucent SAS
Original Assignee
Alcatel CIT SA
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA, Alcatel SA filed Critical Alcatel CIT SA
Application granted granted Critical
Publication of DE3369428D1 publication Critical patent/DE3369428D1/de
Expired legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2224/8319Arrangement of the layer connectors prior to mounting
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    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/135Removal of substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10Methods of surface bonding and/or assembly therefor
    • Y10T156/1089Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
    • Y10T156/1092All laminae planar and face to face
    • Y10T156/1093All laminae planar and face to face with covering of discrete laminae with additional lamina
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49169Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
DE8383103114T 1982-04-01 1983-03-29 Process for encapsulating semi-conductor components and encapsulated components so obtained Expired DE3369428D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8205624A FR2524707B1 (fr) 1982-04-01 1982-04-01 Procede d'encapsulation de composants semi-conducteurs, et composants encapsules obtenus

Publications (1)

Publication Number Publication Date
DE3369428D1 true DE3369428D1 (en) 1987-02-26

Family

ID=9272637

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383103114T Expired DE3369428D1 (en) 1982-04-01 1983-03-29 Process for encapsulating semi-conductor components and encapsulated components so obtained

Country Status (5)

Country Link
US (1) US4530152A (de)
EP (1) EP0091072B1 (de)
JP (1) JPS58182853A (de)
DE (1) DE3369428D1 (de)
FR (1) FR2524707B1 (de)

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IT1202657B (it) * 1987-03-09 1989-02-09 Sgs Microelettronica Spa Procedimento di fabbricazione di un dispositivo modulare di potenza a semiconduttore e dispositivo con esso ottenento
US5032543A (en) * 1988-06-17 1991-07-16 Massachusetts Institute Of Technology Coplanar packaging techniques for multichip circuits
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US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
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DE4141775A1 (de) * 1991-12-18 1993-06-24 Manfred Band Verfahren zur herstellung einer elektronischen schaltung
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US5976912A (en) * 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US6465743B1 (en) 1994-12-05 2002-10-15 Motorola, Inc. Multi-strand substrate for ball-grid array assemblies and method
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FR2524707A1 (fr) 1983-10-07
EP0091072A1 (de) 1983-10-12
EP0091072B1 (de) 1987-01-21
JPS58182853A (ja) 1983-10-25
US4530152A (en) 1985-07-23
FR2524707B1 (fr) 1985-05-31

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