DE3369428D1 - Process for encapsulating semi-conductor components and encapsulated components so obtained - Google Patents
Process for encapsulating semi-conductor components and encapsulated components so obtainedInfo
- Publication number
- DE3369428D1 DE3369428D1 DE8383103114T DE3369428T DE3369428D1 DE 3369428 D1 DE3369428 D1 DE 3369428D1 DE 8383103114 T DE8383103114 T DE 8383103114T DE 3369428 T DE3369428 T DE 3369428T DE 3369428 D1 DE3369428 D1 DE 3369428D1
- Authority
- DE
- Germany
- Prior art keywords
- components
- encapsulated
- conductor
- encapsulating
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H01L2924/181—Encapsulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
- Y10T156/1092—All laminae planar and face to face
- Y10T156/1093—All laminae planar and face to face with covering of discrete laminae with additional lamina
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
- Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
- Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8205624A FR2524707B1 (fr) | 1982-04-01 | 1982-04-01 | Procede d'encapsulation de composants semi-conducteurs, et composants encapsules obtenus |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3369428D1 true DE3369428D1 (en) | 1987-02-26 |
Family
ID=9272637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8383103114T Expired DE3369428D1 (en) | 1982-04-01 | 1983-03-29 | Process for encapsulating semi-conductor components and encapsulated components so obtained |
Country Status (5)
Country | Link |
---|---|
US (1) | US4530152A (de) |
EP (1) | EP0091072B1 (de) |
JP (1) | JPS58182853A (de) |
DE (1) | DE3369428D1 (de) |
FR (1) | FR2524707B1 (de) |
Families Citing this family (217)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI72409C (fi) * | 1984-03-09 | 1987-05-11 | Lohja Ab Oy | Foerfarande foer inkapsling av pao en baerremsa anordnade halvledarkomponenter. |
JPS6149432A (ja) * | 1984-08-18 | 1986-03-11 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
IT1202657B (it) * | 1987-03-09 | 1989-02-09 | Sgs Microelettronica Spa | Procedimento di fabbricazione di un dispositivo modulare di potenza a semiconduttore e dispositivo con esso ottenento |
US5032543A (en) * | 1988-06-17 | 1991-07-16 | Massachusetts Institute Of Technology | Coplanar packaging techniques for multichip circuits |
US5008997A (en) * | 1988-09-16 | 1991-04-23 | National Semiconductor | Gold/tin eutectic bonding for tape automated bonding process |
US5200362A (en) * | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
US5293072A (en) * | 1990-06-25 | 1994-03-08 | Fujitsu Limited | Semiconductor device having spherical terminals attached to the lead frame embedded within the package body |
US5446620A (en) * | 1990-08-01 | 1995-08-29 | Staktek Corporation | Ultra high density integrated circuit packages |
US5377077A (en) * | 1990-08-01 | 1994-12-27 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
AU8519891A (en) * | 1990-08-01 | 1992-03-02 | Staktek Corporation | Ultra high density integrated circuit packages, method and apparatus |
US5367766A (en) * | 1990-08-01 | 1994-11-29 | Staktek Corporation | Ultra high density integrated circuit packages method |
US5475920A (en) * | 1990-08-01 | 1995-12-19 | Burns; Carmen D. | Method of assembling ultra high density integrated circuit packages |
FR2666173A1 (fr) * | 1990-08-21 | 1992-02-28 | Thomson Csf | Structure hybride d'interconnexion de circuits integres et procede de fabrication. |
DE4141775A1 (de) * | 1991-12-18 | 1993-06-24 | Manfred Band | Verfahren zur herstellung einer elektronischen schaltung |
US5273940A (en) * | 1992-06-15 | 1993-12-28 | Motorola, Inc. | Multiple chip package with thinned semiconductor chips |
US5344795A (en) * | 1992-09-22 | 1994-09-06 | Microelectronics And Computer Technology Corporation | Method for encapsulating an integrated circuit using a removable heatsink support block |
US5497032A (en) * | 1993-03-17 | 1996-03-05 | Fujitsu Limited | Semiconductor device and lead frame therefore |
US5801437A (en) * | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
US5644161A (en) * | 1993-03-29 | 1997-07-01 | Staktek Corporation | Ultra-high density warp-resistant memory module |
US5369056A (en) * | 1993-03-29 | 1994-11-29 | Staktek Corporation | Warp-resistent ultra-thin integrated circuit package fabrication method |
GB9401770D0 (en) * | 1994-01-31 | 1994-03-23 | Philips Electronics Uk Ltd | Manufacture of electronic devices comprising thin-film circuits |
US5976912A (en) * | 1994-03-18 | 1999-11-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
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Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3371148A (en) * | 1966-04-12 | 1968-02-27 | Radiation Inc | Semiconductor device package and method of assembly therefor |
US3689336A (en) * | 1971-01-04 | 1972-09-05 | Sylvania Electric Prod | Fabrication of packages for integrated circuits |
US3739462A (en) * | 1971-01-06 | 1973-06-19 | Texas Instruments Inc | Method for encapsulating discrete semiconductor chips |
CA1003122A (en) * | 1973-04-30 | 1977-01-04 | Lewis H. Trevail | Method of making multiple isolated semiconductor chip units |
US3959874A (en) * | 1974-12-20 | 1976-06-01 | Western Electric Company, Inc. | Method of forming an integrated circuit assembly |
JPS51138179A (en) * | 1975-05-23 | 1976-11-29 | Seiko Instr & Electronics Ltd | Semi-conductor device |
DE2543968A1 (de) * | 1975-10-02 | 1977-04-07 | Licentia Gmbh | Integrierte schaltungsanordnung |
IT7819031A0 (it) * | 1977-02-24 | 1978-01-04 | Rca Corp | Metodo per la fabbricazione di un dispositivo semiconduttore. |
JPS53149763A (en) * | 1977-06-01 | 1978-12-27 | Citizen Watch Co Ltd | Mounting method of semiconductor integrate circuit |
GB2046024B (en) * | 1979-03-30 | 1983-01-26 | Ferranti Ltd | Circuit assembly |
-
1982
- 1982-04-01 FR FR8205624A patent/FR2524707B1/fr not_active Expired
-
1983
- 1983-03-29 DE DE8383103114T patent/DE3369428D1/de not_active Expired
- 1983-03-29 EP EP83103114A patent/EP0091072B1/de not_active Expired
- 1983-03-31 JP JP58056817A patent/JPS58182853A/ja active Pending
- 1983-04-01 US US06/481,523 patent/US4530152A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2524707A1 (fr) | 1983-10-07 |
EP0091072A1 (de) | 1983-10-12 |
EP0091072B1 (de) | 1987-01-21 |
JPS58182853A (ja) | 1983-10-25 |
US4530152A (en) | 1985-07-23 |
FR2524707B1 (fr) | 1985-05-31 |
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