DE3218974A1 - Leiterverbindungsschicht fuer halbleitervorrichtungen und verfahren zu ihrer herstellung - Google Patents

Leiterverbindungsschicht fuer halbleitervorrichtungen und verfahren zu ihrer herstellung

Info

Publication number
DE3218974A1
DE3218974A1 DE19823218974 DE3218974A DE3218974A1 DE 3218974 A1 DE3218974 A1 DE 3218974A1 DE 19823218974 DE19823218974 DE 19823218974 DE 3218974 A DE3218974 A DE 3218974A DE 3218974 A1 DE3218974 A1 DE 3218974A1
Authority
DE
Germany
Prior art keywords
production
semiconductor devices
connection layer
conductor connection
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19823218974
Other languages
German (de)
English (en)
Other versions
DE3218974C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Yutaka Funada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3218974A1 publication Critical patent/DE3218974A1/de
Application granted granted Critical
Publication of DE3218974C2 publication Critical patent/DE3218974C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19823218974 1981-05-20 1982-05-19 Leiterverbindungsschicht fuer halbleitervorrichtungen und verfahren zu ihrer herstellung Granted DE3218974A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7740181A JPS57192047A (en) 1981-05-20 1981-05-20 Wiring layer in semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
DE3218974A1 true DE3218974A1 (de) 1982-12-16
DE3218974C2 DE3218974C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-05-14

Family

ID=13632873

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19823218974 Granted DE3218974A1 (de) 1981-05-20 1982-05-19 Leiterverbindungsschicht fuer halbleitervorrichtungen und verfahren zu ihrer herstellung

Country Status (2)

Country Link
JP (1) JPS57192047A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3218974A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0119497A1 (en) * 1983-02-22 1984-09-26 Kabushiki Kaisha Toshiba Method of forming electrode/wiring layer
DE3314879A1 (de) * 1983-04-25 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von stabilen, niederohmigen kontakten in integrierten halbleiterschaltungen
DE3702187A1 (de) * 1986-01-27 1987-07-30 Canon Kk Verfahren zur herstellung eines photosensors

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06820Y2 (ja) * 1986-01-22 1994-01-05 株式会社日立製作所 アクテイブマトリクス基板
JP2955814B2 (ja) * 1994-01-24 1999-10-04 エルジイ・セミコン・カンパニイ・リミテッド シリサイドプラグ形成方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5131189A (ja) * 1974-09-11 1976-03-17 Sony Corp Handotaisochi
JPS5521131A (en) * 1978-08-01 1980-02-15 Seiko Epson Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Geipel, H.J., Jr.: Composite Silicide Gate Electrodes-Interconnections for VLSI Technologies,In: IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, Aug. 1980, S. 1417-1424 *
Murarka, S.P.. Refractery Silicides for integrated circuits. In: J. Vac. Sci. Technol. 17(4), Jul/Aug 1980, S. 775-792 *
Rideout, V.L.: Reducing the Sheet Resistance... Circuits. In: IBM TDB, Vol. 17, No. 6, Nov. 1974, S. 1831-1833 *
Tsang, P.J.: Forming Thick Metal Silicide for Contact Barrier. In: IBM TDB, Vol. 19, No. 9, Feb. 1977, S. 3383-3385 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0119497A1 (en) * 1983-02-22 1984-09-26 Kabushiki Kaisha Toshiba Method of forming electrode/wiring layer
US4538344A (en) * 1983-02-22 1985-09-03 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming electrode/wiring layer
DE3314879A1 (de) * 1983-04-25 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von stabilen, niederohmigen kontakten in integrierten halbleiterschaltungen
DE3702187A1 (de) * 1986-01-27 1987-07-30 Canon Kk Verfahren zur herstellung eines photosensors

Also Published As

Publication number Publication date
DE3218974C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-05-14
JPS57192047A (en) 1982-11-26

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Legal Events

Date Code Title Description
OR8 Request for search as to paragraph 43 lit. 1 sentence 1 patent law
8105 Search report available
8110 Request for examination paragraph 44
D2 Grant after examination
8363 Opposition against the patent
8320 Willingness to grant licenses declared (paragraph 23)
8331 Complete revocation