DE3104432C2 - MOS-Transistorschaltung mit Abschaltfunktion - Google Patents

MOS-Transistorschaltung mit Abschaltfunktion

Info

Publication number
DE3104432C2
DE3104432C2 DE3104432A DE3104432A DE3104432C2 DE 3104432 C2 DE3104432 C2 DE 3104432C2 DE 3104432 A DE3104432 A DE 3104432A DE 3104432 A DE3104432 A DE 3104432A DE 3104432 C2 DE3104432 C2 DE 3104432C2
Authority
DE
Germany
Prior art keywords
transistor
mos transistor
circuit
threshold voltage
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3104432A
Other languages
German (de)
English (en)
Other versions
DE3104432A1 (de
Inventor
Shoji Tokyo Ariizumi
Makoto Yokohama Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of DE3104432A1 publication Critical patent/DE3104432A1/de
Application granted granted Critical
Publication of DE3104432C2 publication Critical patent/DE3104432C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Electronic Switches (AREA)
DE3104432A 1980-02-06 1981-02-04 MOS-Transistorschaltung mit Abschaltfunktion Expired DE3104432C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1330280A JPS56111180A (en) 1980-02-06 1980-02-06 Semiconductor device

Publications (2)

Publication Number Publication Date
DE3104432A1 DE3104432A1 (de) 1981-12-24
DE3104432C2 true DE3104432C2 (de) 1982-10-21

Family

ID=11829380

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3104432A Expired DE3104432C2 (de) 1980-02-06 1981-02-04 MOS-Transistorschaltung mit Abschaltfunktion

Country Status (4)

Country Link
US (1) US4384220A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS56111180A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3104432C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB2069273B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19905749B4 (de) * 1998-02-12 2004-04-29 LG Semicon Co., Ltd., Cheongju Bereitschaftsschaltung mit verringerter Stromaufnahme

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542485A (en) * 1981-01-14 1985-09-17 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit
JPS57172586A (en) * 1981-04-16 1982-10-23 Toshiba Corp Semiconductor integrated circuit
US4481432A (en) * 1982-06-07 1984-11-06 Fairchild Camera & Instrument Corp. Programmable output buffer
JPS5957525A (ja) * 1982-09-28 1984-04-03 Fujitsu Ltd Ｃｍｉｓ回路装置
US4467455A (en) * 1982-11-01 1984-08-21 Motorola, Inc. Buffer circuit
US4521698A (en) * 1982-12-02 1985-06-04 Mostek Corporation Mos output driver circuit avoiding hot-electron effects
US4484088A (en) * 1983-02-04 1984-11-20 General Electric Company CMOS Four-transistor reset/set latch
DE3329874A1 (de) * 1983-08-18 1985-03-07 Siemens AG, 1000 Berlin und 8000 München Mos-inverterschaltung
US4503341A (en) * 1983-08-31 1985-03-05 Texas Instruments Incorporated Power-down inverter circuit
US4631426A (en) * 1984-06-27 1986-12-23 Honeywell Inc. Digital circuit using MESFETS
JPS6199413A (ja) * 1984-10-19 1986-05-17 Mitsubishi Electric Corp 出力回路装置
JPS6240697A (ja) * 1985-08-16 1987-02-21 Fujitsu Ltd 半導体記憶装置
FR2607338A1 (fr) * 1986-11-21 1988-05-27 Eurotechnique Sa Circuit de commutation de tension en technologie mos
JPH0197016A (ja) * 1987-10-09 1989-04-14 Fujitsu Ltd 半導体集積回路装置
GB2222045B (en) * 1988-08-19 1993-04-07 Motorola Inc Transistor breakdown protection circuit
US5057715A (en) * 1988-10-11 1991-10-15 Intel Corporation CMOS output circuit using a low threshold device
US4968900A (en) * 1989-07-31 1990-11-06 Harris Corporation Programmable speed/power arrangement for integrated devices having logic matrices
US5463603A (en) * 1992-03-18 1995-10-31 Imp, Inc. Computer disk drive integrated data path circuit optimized for handling both data and servo signals
JPH08148986A (ja) * 1994-11-21 1996-06-07 Mitsubishi Electric Corp 出力バッファ回路
US6078194A (en) * 1995-11-13 2000-06-20 Vitesse Semiconductor Corporation Logic gates for reducing power consumption of gallium arsenide integrated circuits
US5999017A (en) * 1997-07-03 1999-12-07 Motorola, Inc. CMOS implemented output buffer circuit for providing ECL level signals
US6137318A (en) * 1997-12-09 2000-10-24 Oki Electric Industry Co., Ltd. Logic circuit having dummy MOS transistor
US7619463B2 (en) * 2005-02-17 2009-11-17 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Power down circuit
KR100801961B1 (ko) * 2006-05-26 2008-02-12 한국전자통신연구원 듀얼 게이트 유기트랜지스터를 이용한 인버터
KR100790761B1 (ko) * 2006-09-29 2008-01-03 한국전자통신연구원 인버터
KR100816498B1 (ko) * 2006-12-07 2008-03-24 한국전자통신연구원 표면 처리된 층을 포함하는 유기 인버터 및 그 제조 방법
KR101353212B1 (ko) * 2011-06-14 2014-01-22 한국과학기술원 인버터 및 인버터가 구비된 스위칭회로
CN114898790A (zh) 2016-01-29 2022-08-12 三星电子株式会社 用于选择性地执行隔离功能的半导体器件及其布局替代方法
CN107039070B (zh) 2016-01-29 2022-06-14 三星电子株式会社 用于选择性地执行隔离功能的半导体器件及其布局替代方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4094012A (en) * 1976-10-01 1978-06-06 Intel Corporation Electrically programmable MOS read-only memory with isolated decoders
US4096584A (en) * 1977-01-31 1978-06-20 Intel Corporation Low power/high speed static ram
US4264828A (en) * 1978-11-27 1981-04-28 Intel Corporation MOS Static decoding circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19905749B4 (de) * 1998-02-12 2004-04-29 LG Semicon Co., Ltd., Cheongju Bereitschaftsschaltung mit verringerter Stromaufnahme

Also Published As

Publication number Publication date
DE3104432A1 (de) 1981-12-24
JPS6129068B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1986-07-04
JPS56111180A (en) 1981-09-02
GB2069273B (en) 1983-10-05
US4384220A (en) 1983-05-17
GB2069273A (en) 1981-08-19

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: H03K 19/096

8126 Change of the secondary classification

Free format text: G11C 7/00 H03K 19/20

D2 Grant after examination
8327 Change in the person/name/address of the patent owner

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Free format text: FRHR. VON UEXKUELL, J., DIPL.-CHEM. DR.RER.NAT. GRAF ZU STOLBERG-WERNIGERODE, U., DIPL.-CHEM. DR.RER.NAT. SUCHANTKE, J., DIPL.-ING. HUBER, A., DIPL.-ING. VON KAMEKE, A., DIPL.-CHEM. DR.RER.NAT., PAT.-ANW., 2000 HAMBURG

8328 Change in the person/name/address of the agent

Free format text: STOLBERG-WERNIGERODE, GRAF ZU, U., DIPL.-CHEM. DR.RER.NAT. SUCHANTKE, J., DIPL.-ING. HUBER, A., DIPL.-ING. KAMEKE, VON, A., DIPL.-CHEM. DR.RER.NAT., 2000 HAMBURG SCHULMEYER, K., DIPL.-CHEM. DR.RER.NAT., PAT.-ANWAELTE, 2087 HASLOH

8339 Ceased/non-payment of the annual fee