DE2708637C3 - Schaltungsanordnung zur Bildung einer BCD-Summe oder einer reinen Binär-Summe aus einem ersten und einem zweiten Operanden - Google Patents

Schaltungsanordnung zur Bildung einer BCD-Summe oder einer reinen Binär-Summe aus einem ersten und einem zweiten Operanden

Info

Publication number
DE2708637C3
DE2708637C3 DE19772708637 DE2708637A DE2708637C3 DE 2708637 C3 DE2708637 C3 DE 2708637C3 DE 19772708637 DE19772708637 DE 19772708637 DE 2708637 A DE2708637 A DE 2708637A DE 2708637 C3 DE2708637 C3 DE 2708637C3
Authority
DE
Germany
Prior art keywords
bcd
binary
carry
circuit
sum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19772708637
Other languages
German (de)
English (en)
Other versions
DE2708637B2 (de
DE2708637A1 (de
Inventor
Jack Lee Scottsdale Ariz. Anderson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE2708637A1 publication Critical patent/DE2708637A1/de
Publication of DE2708637B2 publication Critical patent/DE2708637B2/de
Application granted granted Critical
Publication of DE2708637C3 publication Critical patent/DE2708637C3/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921—Single digit adding or subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
DE19772708637 1976-03-08 1977-02-28 Schaltungsanordnung zur Bildung einer BCD-Summe oder einer reinen Binär-Summe aus einem ersten und einem zweiten Operanden Expired DE2708637C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66446076A 1976-03-08 1976-03-08

Publications (3)

Publication Number Publication Date
DE2708637A1 DE2708637A1 (de) 1977-09-15
DE2708637B2 DE2708637B2 (de) 1980-06-19
DE2708637C3 true DE2708637C3 (de) 1985-07-18

Family

ID=24666056

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19772708637 Expired DE2708637C3 (de) 1976-03-08 1977-02-28 Schaltungsanordnung zur Bildung einer BCD-Summe oder einer reinen Binär-Summe aus einem ersten und einem zweiten Operanden

Country Status (4)

Country Link
JP (1) JPS52108745A (enExample)
DE (1) DE2708637C3 (enExample)
FR (1) FR2344071A1 (enExample)
GB (1) GB1525893A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09231055A (ja) * 1996-02-27 1997-09-05 Denso Corp 論理演算回路及びキャリールックアヘッド加算器

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3112396A (en) * 1957-05-03 1963-11-26 Ibm Arithmetic circuitry
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system

Also Published As

Publication number Publication date
DE2708637B2 (de) 1980-06-19
FR2344071A1 (fr) 1977-10-07
FR2344071B1 (enExample) 1981-10-02
GB1525893A (en) 1978-09-20
JPS52108745A (en) 1977-09-12
JPS5534454B2 (enExample) 1980-09-06
DE2708637A1 (de) 1977-09-15

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Legal Events

Date Code Title Description
8281 Inventor (new situation)

Free format text: ANDERSON, JACK LEE, SCOTTSDALE, ARIZ., US

C3 Grant after two publication steps (3rd publication)