GB1525893A - Adder for summing bcd operands with precorrected result - Google Patents

Adder for summing bcd operands with precorrected result

Info

Publication number
GB1525893A
GB1525893A GB363277A GB363277A GB1525893A GB 1525893 A GB1525893 A GB 1525893A GB 363277 A GB363277 A GB 363277A GB 363277 A GB363277 A GB 363277A GB 1525893 A GB1525893 A GB 1525893A
Authority
GB
United Kingdom
Prior art keywords
adder
carry
signal
circuit
sum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB363277A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of GB1525893A publication Critical patent/GB1525893A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921—Single digit adding or subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)

Abstract

1525893 Adders MOTOROLA Inc 28 Jan 1977 [8 March 1976] 03632/77 Heading G4A An adder circuit for two binary coded decimal digits A, B includes an adder 12 forming the sum of the two digits (without carry-in), a pre-correction circuit 48 adding six or zero to the sum in dependence on whether it is greater than nine or not and an incrementer 62 incrementing the output of the circuit 48 in response to a carry-in signal. As described look ahead carry logic external to the adder generates a carry-in signal if carry generate and propagate circuit 30 of the adder for the next lower digit generates a carry signal on conductor 64. A carry propagate signal is generated on conductor 68 if the sum formed in the adder 12 is nine.
GB363277A 1976-03-08 1977-01-28 Adder for summing bcd operands with precorrected result Expired GB1525893A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66446076A 1976-03-08 1976-03-08

Publications (1)

Publication Number Publication Date
GB1525893A true GB1525893A (en) 1978-09-20

Family

ID=24666056

Family Applications (1)

Application Number Title Priority Date Filing Date
GB363277A Expired GB1525893A (en) 1976-03-08 1977-01-28 Adder for summing bcd operands with precorrected result

Country Status (4)

Country Link
JP (1) JPS52108745A (en)
DE (1) DE2708637C3 (en)
FR (1) FR2344071A1 (en)
GB (1) GB1525893A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0525492Y2 (en) * 1987-01-26 1993-06-28
JPH09231055A (en) * 1996-02-27 1997-09-05 Denso Corp Logical operation circuit and carry look-ahead adder

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3112396A (en) * 1957-05-03 1963-11-26 Ibm Arithmetic circuitry
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system

Also Published As

Publication number Publication date
FR2344071A1 (en) 1977-10-07
DE2708637A1 (en) 1977-09-15
JPS5534454B2 (en) 1980-09-06
JPS52108745A (en) 1977-09-12
DE2708637B2 (en) 1980-06-19
FR2344071B1 (en) 1981-10-02
DE2708637C3 (en) 1985-07-18

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years

Effective date: 19970127