GB1322657A - Adders - Google Patents

Adders

Info

Publication number
GB1322657A
GB1322657A GB1322657DA GB1322657A GB 1322657 A GB1322657 A GB 1322657A GB 1322657D A GB1322657D A GB 1322657DA GB 1322657 A GB1322657 A GB 1322657A
Authority
GB
United Kingdom
Prior art keywords
store
functions
stores
xor
carry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1322657A publication Critical patent/GB1322657A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5057—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using table look-up; using programmable logic arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4804—Associative memory or processor

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

1322657 Adders INTERNATIONAL BUSINESS MACHINES CORP 10 Sept 1971 42238/71 Heading G4A The sum of two operands A, B is produced by two pairs of serially-connected associative stores 20, 21 and 22, 23 of the kind producing read out signals on paired lines for each bit and containing function tables for generating, in the case of stores 20, 22, interim functions and, in the case of stores 21, 23, result functions from the interim functions, store 20 receiving the low order bits of A and B, store 22 receiving the high order bits of A and B, and at least some of the output line pairs of store 20 being connected to at least one of stores 21, 23 through XOR circuits (not shown). Store 20 generates the interim functions Pr = XOR(Ar, Br); Gr = Ar.Br; C L = carry out of the highest low order bit position; C P = carry propagate. Store 22 generates the P, G functions for the high order bits. Stores 21, 23 generate the result bits R N from the supplied functions P, G, C L , C P , and, if necessary a carry-in CI, the overall addition process being defined by R N = XOR (AN, B N , C N-1 ) and C N-1 = A N-1 .B N-1 +C N-2 .XOR(A N-1 , B N-1 ). For the function C L in store 20, a fourth, " unless " state Y is required to cancel a potential carry resulting from A r = B r = 1 when a carry sink A r = B r = 0 exists in a higher bit position, read out of a Y state producing an output on both associated bit lines so that the associated XOR circuit is forced to give a 0 output.
GB1322657D 1971-09-10 1971-09-10 Adders Expired GB1322657A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4223871 1971-09-10

Publications (1)

Publication Number Publication Date
GB1322657A true GB1322657A (en) 1973-07-11

Family

ID=10423492

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1322657D Expired GB1322657A (en) 1971-09-10 1971-09-10 Adders

Country Status (4)

Country Link
JP (1) JPS5526749B2 (en)
DE (1) DE2238687A1 (en)
FR (1) FR2151977A5 (en)
GB (1) GB1322657A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4157590A (en) * 1978-01-03 1979-06-05 International Business Machines Corporation Programmable logic array adder
GB2011669B (en) * 1978-01-03 1982-01-13 Ibm Programmable logic array adders
US4241414A (en) * 1979-01-03 1980-12-23 Burroughs Corporation Binary adder employing a plurality of levels of individually programmed PROMS
JPS5960617A (en) * 1982-09-30 1984-04-06 Fujitsu Denso Ltd Resonant type constant-current circuit

Also Published As

Publication number Publication date
JPS5526749B2 (en) 1980-07-15
FR2151977A5 (en) 1973-04-20
JPS4838038A (en) 1973-06-05
DE2238687A1 (en) 1973-03-22

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee