DE2637310A1 - Verfahren zur herstellung von monolithisch integrierten halbleiterschaltungen mit herabgesetzter streukapazitaet - Google Patents

Verfahren zur herstellung von monolithisch integrierten halbleiterschaltungen mit herabgesetzter streukapazitaet

Info

Publication number
DE2637310A1
DE2637310A1 DE19762637310 DE2637310A DE2637310A1 DE 2637310 A1 DE2637310 A1 DE 2637310A1 DE 19762637310 DE19762637310 DE 19762637310 DE 2637310 A DE2637310 A DE 2637310A DE 2637310 A1 DE2637310 A1 DE 2637310A1
Authority
DE
Germany
Prior art keywords
oxide layer
diffusion
thickness
foreign atoms
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19762637310
Other languages
German (de)
English (en)
Inventor
Robert Michael Quinn
William John Schuele
Richard Alan Unis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2637310A1 publication Critical patent/DE2637310A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only
    • H10P32/141—
    • H10P32/171—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/157—Special diffusion and profiles

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
DE19762637310 1975-09-05 1976-08-19 Verfahren zur herstellung von monolithisch integrierten halbleiterschaltungen mit herabgesetzter streukapazitaet Withdrawn DE2637310A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/610,722 US3975220A (en) 1975-09-05 1975-09-05 Diffusion control for controlling parasitic capacitor effects in single FET structure arrays

Publications (1)

Publication Number Publication Date
DE2637310A1 true DE2637310A1 (de) 1977-03-10

Family

ID=24446154

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762637310 Withdrawn DE2637310A1 (de) 1975-09-05 1976-08-19 Verfahren zur herstellung von monolithisch integrierten halbleiterschaltungen mit herabgesetzter streukapazitaet

Country Status (4)

Country Link
US (1) US3975220A (enExample)
JP (1) JPS5232684A (enExample)
DE (1) DE2637310A1 (enExample)
FR (1) FR2323227A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012863A3 (en) * 1978-12-26 1980-10-15 International Business Machines Corporation Method of making semiconductor devices with reduced parasitic capacitance

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5681968A (en) * 1979-12-07 1981-07-04 Toshiba Corp Manufacture of semiconductor device
KR0167271B1 (ko) * 1995-11-30 1998-12-15 문정환 비균등 도우프 채널 구조를 갖는 반도체소자의 제조방법
US6057203A (en) * 1998-06-19 2000-05-02 Programmable Silicon Solutions Integrated circuit capacitor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3574010A (en) * 1968-12-30 1971-04-06 Texas Instruments Inc Fabrication of metal insulator semiconductor field effect transistors
US3604107A (en) * 1969-04-17 1971-09-14 Collins Radio Co Doped oxide field effect transistors
US3690969A (en) * 1971-05-03 1972-09-12 Motorola Inc Method of doping semiconductor substrates
US3926694A (en) * 1972-07-24 1975-12-16 Signetics Corp Double diffused metal oxide semiconductor structure with isolated source and drain and method
JPS567304B2 (enExample) * 1972-08-28 1981-02-17
US3811076A (en) * 1973-01-02 1974-05-14 Ibm Field effect transistor integrated circuit and memory
US3841926A (en) * 1973-01-02 1974-10-15 Ibm Integrated circuit fabrication process
US3873372A (en) * 1973-07-09 1975-03-25 Ibm Method for producing improved transistor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012863A3 (en) * 1978-12-26 1980-10-15 International Business Machines Corporation Method of making semiconductor devices with reduced parasitic capacitance

Also Published As

Publication number Publication date
FR2323227B1 (enExample) 1979-05-04
JPS5232684A (en) 1977-03-12
US3975220A (en) 1976-08-17
FR2323227A1 (fr) 1977-04-01

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee