DE2550275C2 - Verfahren zum Herstellen von Barrieren für Lötzinn auf Leiterzügen - Google Patents

Verfahren zum Herstellen von Barrieren für Lötzinn auf Leiterzügen

Info

Publication number
DE2550275C2
DE2550275C2 DE2550275A DE2550275A DE2550275C2 DE 2550275 C2 DE2550275 C2 DE 2550275C2 DE 2550275 A DE2550275 A DE 2550275A DE 2550275 A DE2550275 A DE 2550275A DE 2550275 C2 DE2550275 C2 DE 2550275C2
Authority
DE
Germany
Prior art keywords
gold
barriers
glass
solder
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2550275A
Other languages
German (de)
English (en)
Other versions
DE2550275A1 (de
Inventor
Lewis Franklin LaGrangeville N.Y. Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2550275A1 publication Critical patent/DE2550275A1/de
Application granted granted Critical
Publication of DE2550275C2 publication Critical patent/DE2550275C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H05K3/247—Finish coating of conductors by using conductive pastes, inks or powders
    • H05K3/248—Finish coating of conductors by using conductive pastes, inks or powders fired compositions for inorganic substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/017—Glass ceramic coating, e.g. formed on inorganic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2081—Compound repelling a metal, e.g. solder
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Conductive Materials (AREA)
  • Glass Compositions (AREA)
DE2550275A 1974-12-23 1975-11-08 Verfahren zum Herstellen von Barrieren für Lötzinn auf Leiterzügen Expired DE2550275C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/535,261 US4017889A (en) 1974-12-23 1974-12-23 Ternary barrier structure for conductive electrodes

Publications (2)

Publication Number Publication Date
DE2550275A1 DE2550275A1 (de) 1976-07-01
DE2550275C2 true DE2550275C2 (de) 1983-06-01

Family

ID=24133484

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2550275A Expired DE2550275C2 (de) 1974-12-23 1975-11-08 Verfahren zum Herstellen von Barrieren für Lötzinn auf Leiterzügen

Country Status (5)

Country Link
US (1) US4017889A (enExample)
JP (1) JPS5845824B2 (enExample)
DE (1) DE2550275C2 (enExample)
FR (1) FR2296348A1 (enExample)
GB (1) GB1484435A (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54159964U (enExample) * 1978-04-28 1979-11-08
US4611746A (en) * 1984-06-28 1986-09-16 International Business Machines Corporation Process for forming improved solder connections for semiconductor devices with enhanced fatigue life
JPS62141820U (enExample) * 1986-02-28 1987-09-07
JPS62151326U (enExample) * 1986-03-17 1987-09-25
US5532612A (en) * 1994-07-19 1996-07-02 Liang; Louis H. Methods and apparatus for test and burn-in of integrated circuit devices
FR2734983B1 (fr) * 1995-05-29 1997-07-04 Sgs Thomson Microelectronics Utilisation d'un micromodule comme boitier de montage en surface et procede correspondant
US5926731A (en) * 1997-07-02 1999-07-20 Delco Electronics Corp. Method for controlling solder bump shape and stand-off height
US6531663B1 (en) * 1998-01-30 2003-03-11 Delphi Technologies, Inc. Solder stop for an electrical connection and method therefor
JP3756691B2 (ja) * 1999-03-18 2006-03-15 株式会社日立製作所 内燃機関用の樹脂封止形電子装置
US7592202B2 (en) * 2006-03-31 2009-09-22 Intel Corporation Embedding device in substrate cavity
FR2914490B1 (fr) * 2007-03-26 2009-05-29 Commissariat Energie Atomique Procede de soudure de deux elements entre eux au moyen d'un materiau de brasure.

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3339274A (en) * 1964-03-16 1967-09-05 Hughes Aircraft Co Top contact for surface protected semiconductor devices
US3374110A (en) * 1964-05-27 1968-03-19 Ibm Conductive element, composition and method
US3429040A (en) * 1965-06-18 1969-02-25 Ibm Method of joining a component to a substrate
GB1143815A (enExample) * 1965-06-18 1900-01-01
US3495133A (en) * 1965-06-18 1970-02-10 Ibm Circuit structure including semiconductive chip devices joined to a substrate by solder contacts
US3809625A (en) * 1972-08-15 1974-05-07 Gen Motors Corp Method of making contact bumps on flip-chips

Also Published As

Publication number Publication date
US4017889A (en) 1977-04-12
GB1484435A (en) 1977-09-01
DE2550275A1 (de) 1976-07-01
JPS5845824B2 (ja) 1983-10-12
JPS5177862A (enExample) 1976-07-06
FR2296348B1 (enExample) 1978-05-12
FR2296348A1 (fr) 1976-07-23

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Legal Events

Date Code Title Description
OD Request for examination
8128 New person/name/address of the agent

Representative=s name: NEULAND, J., DIPL.-ING., PAT.-ASS., 7030 BOEBLINGE

8126 Change of the secondary classification

Ipc: H01K 3/22

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee