DE2522448A1 - Verfahren zur herstellung einer halbleiteranordnung und durch dieses verfahren hergestellte halbleiteranordnung - Google Patents

Verfahren zur herstellung einer halbleiteranordnung und durch dieses verfahren hergestellte halbleiteranordnung

Info

Publication number
DE2522448A1
DE2522448A1 DE19752522448 DE2522448A DE2522448A1 DE 2522448 A1 DE2522448 A1 DE 2522448A1 DE 19752522448 DE19752522448 DE 19752522448 DE 2522448 A DE2522448 A DE 2522448A DE 2522448 A1 DE2522448 A1 DE 2522448A1
Authority
DE
Germany
Prior art keywords
layer
polycrystalline
zone
parts
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19752522448
Other languages
German (de)
English (en)
Inventor
Keith Nicholas Harlow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE2522448A1 publication Critical patent/DE2522448A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/0133—Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30—Diffusion for doping of conductive or resistive layers
    • H10P32/302—Doping polycrystalline silicon or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
DE19752522448 1974-05-21 1975-05-21 Verfahren zur herstellung einer halbleiteranordnung und durch dieses verfahren hergestellte halbleiteranordnung Withdrawn DE2522448A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2258374A GB1477511A (en) 1974-05-21 1974-05-21 Methods of manufacturing semiconductor devices

Publications (1)

Publication Number Publication Date
DE2522448A1 true DE2522448A1 (de) 1975-12-04

Family

ID=10181779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752522448 Withdrawn DE2522448A1 (de) 1974-05-21 1975-05-21 Verfahren zur herstellung einer halbleiteranordnung und durch dieses verfahren hergestellte halbleiteranordnung

Country Status (6)

Country Link
JP (1) JPS5617826B2 (enExample)
CA (1) CA1040749A (enExample)
DE (1) DE2522448A1 (enExample)
FR (1) FR2272486B1 (enExample)
GB (1) GB1477511A (enExample)
NL (1) NL7505698A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit
JPS598855Y2 (ja) * 1978-09-01 1984-03-19 大阪電気株式会社 ワイヤ送給装置
JPS5546570A (en) * 1978-09-30 1980-04-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Method of fabricating mos semiconductor device
US4298402A (en) * 1980-02-04 1981-11-03 Fairchild Camera & Instrument Corp. Method of fabricating self-aligned lateral bipolar transistor utilizing special masking techniques
JPS6070401U (ja) * 1983-10-24 1985-05-18 株式会社月星製作所 車輪用スポ−ク
CN111665669A (zh) * 2015-01-08 2020-09-15 群创光电股份有限公司 显示面板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5542501B2 (enExample) * 1974-01-29 1980-10-31

Also Published As

Publication number Publication date
JPS5617826B2 (enExample) 1981-04-24
GB1477511A (en) 1977-06-22
FR2272486A1 (enExample) 1975-12-19
NL7505698A (nl) 1975-11-25
JPS51282A (enExample) 1976-01-05
CA1040749A (en) 1978-10-17
FR2272486B1 (enExample) 1979-01-19

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee