CA1040749A - Method of manufacturing fine line conductors on semiconductors - Google Patents
Method of manufacturing fine line conductors on semiconductorsInfo
- Publication number
- CA1040749A CA1040749A CA227,266A CA227266A CA1040749A CA 1040749 A CA1040749 A CA 1040749A CA 227266 A CA227266 A CA 227266A CA 1040749 A CA1040749 A CA 1040749A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- polycrystalline
- diffused
- region
- masking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004020 conductor Substances 0.000 title description 3
- 230000000873 masking effect Effects 0.000 claims abstract description 97
- 238000009792 diffusion process Methods 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 66
- 239000000463 material Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 37
- 230000005669 field effect Effects 0.000 claims description 26
- 238000011282 treatment Methods 0.000 claims description 15
- 239000002019 doping agent Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract description 58
- 239000010703 silicon Substances 0.000 abstract description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 46
- 229910052814 silicon oxide Inorganic materials 0.000 description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 39
- 229910052796 boron Inorganic materials 0.000 description 38
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 37
- 229910052581 Si3N4 Inorganic materials 0.000 description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 28
- 238000000151 deposition Methods 0.000 description 11
- 230000008021 deposition Effects 0.000 description 10
- 238000009740 moulding (composite fabrication) Methods 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- 235000014786 phosphorus Nutrition 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- BSFODEXXVBBYOC-UHFFFAOYSA-N 8-[4-(dimethylamino)butan-2-ylamino]quinolin-6-ol Chemical compound C1=CN=C2C(NC(CCN(C)C)C)=CC(O)=CC2=C1 BSFODEXXVBBYOC-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 241001664469 Tibicina haematodes Species 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000075 oxide glass Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920000136 polysorbate Polymers 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 230000002311 subsequent effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Weting (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
ABSTRACT:
A method of defining, a fine line low resis-tivity pattern in a layer of high resistivity poly-crystalline semiconductor material present on an insulating layer on the surface of a semiconductor body by lateral impurity diffusion under the edge of a masking layer present on the polycrystalline semiconductor material. The undiffused polycrystalline semiconductor material mayor may not subsequently be removed depending upon the application of the method.
In one form the fine line pattern is selectively re-moved to leave a precisely defined aperture of narrow width in the polycrystalline layer. In one specific embodiment described the method is employed to define high impedance load transistors in a silicon gate integrated circuit. In another specific embodiment described the method is employed to define a compact crossing connection between a polycrystalline silicon line on an oxide layer and an underlying diffused con-nection region in a silicon gate integrated circuit.
Figure 1(c) is suitable for publication purposes.
A method of defining, a fine line low resis-tivity pattern in a layer of high resistivity poly-crystalline semiconductor material present on an insulating layer on the surface of a semiconductor body by lateral impurity diffusion under the edge of a masking layer present on the polycrystalline semiconductor material. The undiffused polycrystalline semiconductor material mayor may not subsequently be removed depending upon the application of the method.
In one form the fine line pattern is selectively re-moved to leave a precisely defined aperture of narrow width in the polycrystalline layer. In one specific embodiment described the method is employed to define high impedance load transistors in a silicon gate integrated circuit. In another specific embodiment described the method is employed to define a compact crossing connection between a polycrystalline silicon line on an oxide layer and an underlying diffused con-nection region in a silicon gate integrated circuit.
Figure 1(c) is suitable for publication purposes.
Description
. P B 32ll37 . 29.4.75 , ,~ . . . .
1040~749 . "Improvements in and relating to methods of manufactur-~i ' . .
. ing semiconductor devic0s".
:i , .
.~ . .
This invention relates to 0ethods of manu-~ facturing semi.conductor devices, particularly but not .,~ exclusively semiconductor integrated circuits compris-ing a plurality of insulated gate field effect transis-tors having gate electrodes formed as doped parts of a deposited layer initially of high resistivity poly-crystalline semiconductor material.
In the manufacture of some known semiconduc-tor integrated circuits which comprise a plurality of insulàted gate field effect transistors, a deposited layer of high resistivity polycrystalline silicon has a plurality of discrete portions defined therein and , . . . .
subsequently doped by diffusion, said discrete portions forming gate electrodes of transistors and further ex-~15 tending on an insulating layer on the semiconductor body surface as conductive connection layers between various circuit elements. Such integrated circuits . are commonly referred to as "silicon gate" circuits.
Various techniques exist for defining and doping the .
~: 20 discrete portions in the polycrystalline silicon layer. However one problem encountered is that it :::
~ is difficuLt to define in such a high resistivity :-. .
`~ deposited layer of polycrystalline semiconductor ~ 2 ., : - .
: ~ , . : , , 29.4.75 .
- 1~4~749 , material a pattern having relatively narrow lines and apertures, for example lines and apertures having a - width less than 2 microns and po'ssibly as small as ---' 0.3 micron. Furthermore It is also desired to define ,~ 5 such discrete portions having suitably sloping edges ', in order to avoid cracking and protrusions in a sub-sequently deposited overlying layer.
In some commonly occurring integrated cir-cuits comprising a plurality of insulated gate field effect transistors a memory cell comprises a cross-coupled pair of the transistors. The drain of each transistor of the pair is directly connected to the gate of the other transistor of the pair,and each transistor has a load impedance in series with the sourcë. To keçp the power dissipation low it is es-', sential that the load impedances aré high and for this : .
,~ reason it has been common practice to form theseimpedances as further insulated gate field effect transistors having'their gates connected to their drains. In this manner a load impedance of controlled magnitude can be obtained in a simple manner and oc-; cupy much less area than when formed as a conventional resistor in which the bulk resistivity of a separate ~`J semiconductor region between two ohmlc contacts there-'~ 25 to i9 utilised. However there exists a limit of the : ~i - impedance value that can be obtained in this manner ,~' ' for a given surface area of the semiconductor body :
.~ , ~ .
' PI~B'32437 , 29.4.75 : . .
~ 1040749 occupied by the load transistor.. l'his is due to the fact that for a high impedance value the transi.stor having the gate shorted to the drain should have a is the length of the ~! hlgh w- ratlo where _ channel region between the sourcè and drain regions and w is the width of the d~nel region corresponding sub-stantially to the width of the gate electrode. With conventional processing technology as used for form-ing so-called "silicon gate" circuits there exists a ].ower limit on the value of w that can be repro~
ducibly obtained.
According to th0 invention there is provid-ed a mebhod of manufacturing a semiconductor device in . which a masking layer is formed on part of the surface of a layer of relatively high resistivity polycrystal-line semiconductor material present on an insulating , layer provided at a surface of a semiconductor body or body part and a narrow~ relatively low resistivity ' ' conductive region preferab~y having a substantially uniform narrow line width, is defined in the poly-crystalline layer by substantially laterally intro-ducing,a doping element into a portion of the poly-. crystalline-layer underlying an edge portion of the ~ masking layer and defining a lateral boundary of '~ 25 said relatively low resistivity conductive region ~' on the side of the edge of,the masking layer. The : introduction of the doping element is preferably .
. -- 4 -- , .
' ,' PHB 32437 ,: ` ' ' ' 29.4.75 .. . .
.
carried out by diffusion, although other processes ; such as ion implantation at a small angle with the ,' main body surface may also be used.
- .
Preferably the doping element is prevented from being introduced through the insulating layer into the semiconductor body or body part.
In this method doping of at least one portion of the polycrystalline layer is obtained by lateral diffuslon into a surface masked portion of - the layer whereas with the previously used methods diffusion,is effected directly and transversely in-to an upper surface of an exposed portion of a, poly-crystalline layer. In this manner the line width of :, .
a relatively low resistivity conductive region may be accurately controlled and have a significantly , smaller value than hitherto reproducibly obtain-.~
' ~, able by the previously used methods, Furthermore - a,plurality of such portions having narrow line widths may be obtained having sloping edges of ., . ~ .
~, 20 desired configuration with respect to the subse-.,j .
,,i quent application of further layers by deposition on said portions. In accordance with the kind of ~'~ - device to be manufactured the low resistivity con-. ~ . .
ductive region may be used for various purposes and the non-dlffused portlons of the polycrystalline layer may be either removed or retained as will be ~", , described hereinafter. However in one particular-~` , . " ' ,.
.
~ - 5 , .: ,~ , ,, ~ - PHB 32437
1040~749 . "Improvements in and relating to methods of manufactur-~i ' . .
. ing semiconductor devic0s".
:i , .
.~ . .
This invention relates to 0ethods of manu-~ facturing semi.conductor devices, particularly but not .,~ exclusively semiconductor integrated circuits compris-ing a plurality of insulated gate field effect transis-tors having gate electrodes formed as doped parts of a deposited layer initially of high resistivity poly-crystalline semiconductor material.
In the manufacture of some known semiconduc-tor integrated circuits which comprise a plurality of insulàted gate field effect transistors, a deposited layer of high resistivity polycrystalline silicon has a plurality of discrete portions defined therein and , . . . .
subsequently doped by diffusion, said discrete portions forming gate electrodes of transistors and further ex-~15 tending on an insulating layer on the semiconductor body surface as conductive connection layers between various circuit elements. Such integrated circuits . are commonly referred to as "silicon gate" circuits.
Various techniques exist for defining and doping the .
~: 20 discrete portions in the polycrystalline silicon layer. However one problem encountered is that it :::
~ is difficuLt to define in such a high resistivity :-. .
`~ deposited layer of polycrystalline semiconductor ~ 2 ., : - .
: ~ , . : , , 29.4.75 .
- 1~4~749 , material a pattern having relatively narrow lines and apertures, for example lines and apertures having a - width less than 2 microns and po'ssibly as small as ---' 0.3 micron. Furthermore It is also desired to define ,~ 5 such discrete portions having suitably sloping edges ', in order to avoid cracking and protrusions in a sub-sequently deposited overlying layer.
In some commonly occurring integrated cir-cuits comprising a plurality of insulated gate field effect transistors a memory cell comprises a cross-coupled pair of the transistors. The drain of each transistor of the pair is directly connected to the gate of the other transistor of the pair,and each transistor has a load impedance in series with the sourcë. To keçp the power dissipation low it is es-', sential that the load impedances aré high and for this : .
,~ reason it has been common practice to form theseimpedances as further insulated gate field effect transistors having'their gates connected to their drains. In this manner a load impedance of controlled magnitude can be obtained in a simple manner and oc-; cupy much less area than when formed as a conventional resistor in which the bulk resistivity of a separate ~`J semiconductor region between two ohmlc contacts there-'~ 25 to i9 utilised. However there exists a limit of the : ~i - impedance value that can be obtained in this manner ,~' ' for a given surface area of the semiconductor body :
.~ , ~ .
' PI~B'32437 , 29.4.75 : . .
~ 1040749 occupied by the load transistor.. l'his is due to the fact that for a high impedance value the transi.stor having the gate shorted to the drain should have a is the length of the ~! hlgh w- ratlo where _ channel region between the sourcè and drain regions and w is the width of the d~nel region corresponding sub-stantially to the width of the gate electrode. With conventional processing technology as used for form-ing so-called "silicon gate" circuits there exists a ].ower limit on the value of w that can be repro~
ducibly obtained.
According to th0 invention there is provid-ed a mebhod of manufacturing a semiconductor device in . which a masking layer is formed on part of the surface of a layer of relatively high resistivity polycrystal-line semiconductor material present on an insulating , layer provided at a surface of a semiconductor body or body part and a narrow~ relatively low resistivity ' ' conductive region preferab~y having a substantially uniform narrow line width, is defined in the poly-crystalline layer by substantially laterally intro-ducing,a doping element into a portion of the poly-. crystalline-layer underlying an edge portion of the ~ masking layer and defining a lateral boundary of '~ 25 said relatively low resistivity conductive region ~' on the side of the edge of,the masking layer. The : introduction of the doping element is preferably .
. -- 4 -- , .
' ,' PHB 32437 ,: ` ' ' ' 29.4.75 .. . .
.
carried out by diffusion, although other processes ; such as ion implantation at a small angle with the ,' main body surface may also be used.
- .
Preferably the doping element is prevented from being introduced through the insulating layer into the semiconductor body or body part.
In this method doping of at least one portion of the polycrystalline layer is obtained by lateral diffuslon into a surface masked portion of - the layer whereas with the previously used methods diffusion,is effected directly and transversely in-to an upper surface of an exposed portion of a, poly-crystalline layer. In this manner the line width of :, .
a relatively low resistivity conductive region may be accurately controlled and have a significantly , smaller value than hitherto reproducibly obtain-.~
' ~, able by the previously used methods, Furthermore - a,plurality of such portions having narrow line widths may be obtained having sloping edges of ., . ~ .
~, 20 desired configuration with respect to the subse-.,j .
,,i quent application of further layers by deposition on said portions. In accordance with the kind of ~'~ - device to be manufactured the low resistivity con-. ~ . .
ductive region may be used for various purposes and the non-dlffused portlons of the polycrystalline layer may be either removed or retained as will be ~", , described hereinafter. However in one particular-~` , . " ' ,.
.
~ - 5 , .: ,~ , ,, ~ - PHB 32437
2~ .75 ~: ' , ' .
~ 104~)749 , .
form of the method to be described hereinafter the low resistivity conductive region havlng a substantially uniform line width is selectively removed to leave an aperture of relatively narrow wi.dth, said aperture being required in the further processing for the manu-- facture of a semiconductor device.
In some forms of the method, hereinafter referred to as first main forms, at an edge portion of the masking layer an edge of the po~ycrystalline ~ayer is exposed throughout the thickness of the poly.crystalline layer and diffusion of the doping element is effected laterally into the polycrystal-lile laye.r via the exposed edge portion to form a relatively low resistivity diffused strip portion of substantially uniform width.
: In one such first main form, subsequent to the diffusion process the masking layer is re-, . ~ moved and the polycrystalline layer is subjected to . . an etching treatment to selectively remove the un-diffused portions and thereby leave at said edge of ~ .
the polycrystalline layer the relatively low resis-. tivity diffus.ed strip portion. In some applications, .
~ including one to be described hereinafter, it may ~,., not be necessary to remove the undiff.used portions . and in fact not even necessary to remove the masking : .. . . .
`~ . layer.
In another first main form the diffusion .'': . . ' ~ - 6 , :
~ - lQ4V749 effected into the edge of the polycrystalline layer comprises first diffusing a doping element charac-teristic of ~ne conductivity type followed by diffus-inf a do'ping element characteristic of the opposite - ~ 5 conductivity type in a higher concentration but to a lesser distance laterally in the layer so that a ~-n junction extending s~bstantially in the direction of thickness of thé layer is formed between the outer-most diffused region characteristic of the opposite ' 10 conductivity type and th~e adjoining diffused region character~istic of the one conductivity type of sub-stantially uniform width and situated below the masking layer. Subsequent to this double diffusion process the masking layer may be removed and the polycrystalli~e layer subjected to an etching treat_ ment to selectively remove the outermost diffused `~ - region of the opposite conductivity type and the un-diffused portions of the layer and thereby leave ad-jacent said edge of the polycrystalline layer a rela-tively low resistivity diffused strip portion of the . ~ .
- one conductivity type and of substantially uniform ~; ~ width. In ~this manner it is possible to form a fine line of doped polycrystalline material of the one - condoctivity type having a well defined upper edge ~ 25 without discontinuities.
:~ . - .
In some other forms of the method, herein-after referred to as second main forms, the masking ., . PHB 32437 29.4.75 ' ' ' , ' .
layer is of smaller area than the polycrystalline layer on which it .is present so that.adjacent the edge portion of the masking lay~r the upper surface ofthe polycrystal-line layer is exposed, the diffusion process comprising first diffusing a doping element characteristic of one conductivity type into said exposed surface such that : lateral diffusion of the element occurs under the masking layer and then diffusing a doping element ., : . characteristic of the opposite conductivity type into said exposed surface in a higher concentrat~n - but to a lesser distance laterally in the layer so that a p-n junction extending substantially in the direction of thickness of the layer is formed under the masking layer between the outermost diffused 15 region of the opposite conductivity type and the ad-: . joining diffused region of the one conductivity type ~: ~ of substantially uniform width and extending under , the masking l.ayer. Subsequent to the double diffusion - . process the masking layer may be removed and the polycrystalline layer subjected to an etching treat_ . ment to selectively remove only the relatively narrow - . diffused region of the one conductivity type and ; thereby form in the polycrystaIline layer an aperture of relatively narrow and substantially uniform width.
This form of the method may be employed, for example, in the manufacture of a charge coupled device (CCD) - in which the insulated gate electrodes are formed ' . . .
. - 8 29.4.75 , '' ' ' ' .
:' , ..
from a layer of polycrystalline semiconductor material and apertures of the said relatively narrow and sub-stantially uniform width are formed in the layer to define the electrodes wlth a very close spacing.
One or more of the said first main forms of the method may be employed in the manufacture of ; a semiconductor device comprising at least one in-sulated gate field effect~transistor, the relatively low resistivity diffused strip portion of the poly-crystalline semiconductor layer forming at least part oP the gate electrode of the transistor. This method of forming the transistor may have significant advantages where it is desired to have a narrow chan-, nel region, that is a gate electrode in the form of ~ 15 a narrow strip, a~ will be described hereinafter in :,.~ , , : connection with one specific embodiment.
J.
~l In one form of such a method in which sub-.. .! : . .
sequènt to the diffusion process the masking layer - is removed and the polycrystalline layer is subjected to a selective etching treatment to remove the undif-fused portions of the polycrystalline layer, subse-quent to the selective etching at least parts of the source and drain regions of the transistor are formed -~ by impurity lntroduction into lhe semiconductor body at opposite sides of the diffused strip portion of the polycrystalline layer, said strip portion mask-ing against impurity introduction into the portion ~ ', .,, " ~ ' .
: _ g 29.4.75 104~)749 of the semicondu.ctor body lying below said strip portion.
In this self-registered method of forming the source and drain regions the said impurity introduction may be effected by ion implantation, for example, by im-planting ions through the insulating layer present on the semiconductor body surface on opposite sides of the said diffused strip portion of the polycrystal-line layer.
The semiconductor device manufactured by one of the said first main forms of the method may be an integrated circuit comprising a plurality of insulated gate field effect transistors having thei~ gate electrodes formed by doped portions of the poly-crystalline semiconductor layer, the said insulated : . 15 gate field effect transistor in which the diffused strip portion constitutes at least part of the gate : -. electrode being formed as a resistive load transis-tor and having the gate electrode connected to the ; drain region. In this manner a high load impedance may be obtained by using such a transistor because the provision of the gate electrode at least in part by the diffused strip portion of the polycrystal-. . ~
line layer enables a high w~' ratio to be obtained.
Such.an integrated circuit may comprise two of the transistors formed as resistive loads and having their gate electrodes connected to a com-` mon drain region, the gate electrodes of said two _ 10 : 29.4.75 . . .~
, . . .. .
104~)749 ~ transistors comprising laterally diffused strip - portions of the polycrystalline layer of substan-tially uniform wldths and situated at opposite edges of a single part of t~e polycrrstalline layer. When ,, in such an integrated circuit the semiconductor body is of silicon and the deposited polycrystalline layer is also of silicon, the method in accordance with the invention may be employed in such manner that the departure from conventionally employed "silicon gate"
processing is minimal and effectively may only involve ,.. . .
the addition of one non-critical masking stage as will .; be described hereina~ter in connection with a specific embodiment of such a method.
.Thus in the said circuit comprising the said ; 15` two load transistors the diffusion to form the gate electrode strip portions of the polycrystalline layer ~ ~ may be effected in the presence of a masking layer '': ~ ' ' ' ' locally present on said part of the polycrystalline layer, said diffusion being carried out simultaneous-ly with the diffusion to form at least part of the source and drain regions of the transistors and to , ~ : . . .
render more highly conductive other exposed portions of the polycrystalline layer, for example portions which are to constitute gate electrodes of other ` : :
transistors in the integrated circuit.
~ The said masking layer locally present on :- . . .
~-~ said part of the polycrystalline layer may comprise .: ... .
; ' , .
.....
.
.~ .
, , PHB 32437 29.4.75 .
~04~749 a residual part of a layer provided at the surface of the polycrystalline layer and employed for the previous definition of the polycrystalline layer into a plura-lity of discrete parts, for example a layer of silicon oxide or silicon nitride.
.. . The method may be employed in the manufacture of a semiconductor device in the form of an integrated . circuit in which at least one portion of the poly-crystalline semiconductor layer constitutes a conduc-tive track which crosses and i9 insulated from an un-. derlying diffused connection region in the semicon--1 ductor body, the opposite edge portions of the track : at the area of the crossing being converted into low resistivity diffused strip portions by the said - 15 lateral diffusion in the presence of a masking layer on the track at the area of the crossing.
~: . In this manner a compact crossing connection can be achieved and this may be incorporated in con-ventional ~silicon gate~ processing by the addition of a single non-critical mask alignment stage and ~ .
only one additional diffusion step.
In one form of such an integrated circuit ~ including a crossing Or t~is configuration the in-:: .
: tegrated circuit comprises a plurality of insulated gate field effect transistors having their gate elec-`~ trodes formed by doped portions of the polycrystalline , semiconductor layer, the method being employed such , PHB 32437 29.4.75 .. . . . .
. ~ ,, ~ . , -that the said diffusion is carried out to form at least part of the source and drain regions of transistors and to dope exposed up~er surface portions of the polycrystalline semiconductor layer. - -In one form of the method in which the lateral .
diffusion is employed to form low resistivity diffused strip portions of a conductive track, subsequent to ~' forming the low resistivity diffused strip portions ', , at the opposite edge portions of the track at the ~ 10 area of the crossing, the undiffused central portion ', of the track at the area of the crossing is selective~
~, ly removed and a further diffusion is carried out to '~, form at the area of the crossing a diffused surface "' ~ region in the semiconductor body in the f,orm of a ; 15 strip situated,intermediate the portions of the body ~ .. . . .
'~ above'which th,e low resistivity diffused strip ~: .
~, portions of the track are present, said diffused . . .
~, - surface region forming part of the diffused con- , :,............ :
nection region. In some embodiments this further ' Z0 diffusion step is also carried out to form at the area of the crossing diffused surface regions in the , .. . .
' ~ semiconductor body situated adjacent and extending :: . - .
'' inwardly below the said oppositç edges of the'track ', at which the low resistivity diffused strip portions . . .
have been formed, said diffused surface regions form-,~ ing parts of the diffused connection region. It is `-' ' not necessary that the last mentioned diffused surface :.. ,:, .
, - - 1~ , .
. ~, .
, Z9.4.75 .
- ~040749 regions shouid extend in contact with the intermediate-ly situated diffused strip region but only necessary that the spacing and the resistivity ~ the adjoining material of the body should be such that in operation the depletion layers associated ~th the junctions be-tween these regions and the adjoining material of the body meet to establish the continuity of the diffused connection region. Preferably the spacing and the re-sistivity are such that the depletion layers meet with no applied bias across the junctions.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which:
, Figures l(a) to 1(e) show in cross-section part of a semiconductor body and applied layérs dur-ing successive sbages in a first embodiment of the method in accordance with the invention;
` Figures 2(a) to 2(c) show in cross-section part of a semiconductor body and applied layers dur-ing successive stages in a second embodiment of the method in accordance with the invention;
Figures 3(a) and 3(b) show in plan view and in cross-section respectively part of a semi-conductor body and applied lay~rs during a stage in ~ 25 . the manufacture of a device comprising an insulated - gate field effect transistor by a method in accord-ance with the invention and Figure 3(c) shows in .
-29.4.75 .'' ~0407~9 cross-section said semiconductor body at a later.stage in the manufacture; .
,~ , Figures 4(a) and 4(b) show in cross-section ' part of a semiconductor body and applied layers during 5 various stages in a further embodiment of ~the method ~', . in accordance with the invention;
. , .
Figures 5(a) and 5(b) show in plan view and cross-section respectively part of the semicon-. ductor body and applied layers of a prior art "silicon gate" integrated circuit in which an insulat-: ed gate field effect transistor having its gate elec-,, .
,' , trode shorted to the drain region is used as & load .'~ ' impedance; ~ , Figure 6 is a circuit diagram showing part of a memor,y cell formed in a known integrated cir-.. - cuit, the memory cell including a cross-coupled pair ., J ~ . ~
.~ ~ of insulated gate field effect transistors each hav-' : - ing in series wi'th i,ts source a load impedance con-~ , . .
',, stituted by an insulated gate field effect t~ansistor having its gate electrode shorted to the drain region;
, Figure 7 shows in plan view part of a semi- .
.
;', conductor body in which the load transistors shown in .
.~ the circuit diagram of Figure 6 are present in in-. A ~ . . .
.' . . tegrated form and obtained by a method in accordance with the invention,;
Figures 8, 9 and 10 are cross-sectional .
views along the lines YIII - VIII, IX - IX and X - X
, , 29.4.75 104~749 respectively in Figure 7;
Figure 11.shows in plan view part of a semi-conductor body of a further integrated circuit compris-ing a plurality of insulated gate field effect transis-tors; and Figures 12 and 13 are cross~sectional views al~ng the lines XII - XII and XIII - XIII respective-ly in Figure 11.
Referring now to Figure 1 there will be described in general outline one illustrative embo-diment of the method in accordance with the invention.
On the surface o~ an n-type silicon substrate 1 of 250 microns thiokness and 4 ohm-cm. resistivity there is thermally grown a silicon oxide layer 2 of 0.1 micron thickness by any conventionally employed method. On the surface of the silicon oxide layer there is de-posited a layer of high resistivity polycrystalline silicon 3 of o.6 micron thickness, this layer being provided by any commonly used method. On the surface of the polycrystalline silicon lauer 3 there is de-posited a masking layer of silicon nitride 4 of 0.2 micron thickness. By first depositing a further mask-ing silicon oxide layer (not shown) and then carrying out a photomasking and etching process an aperture of 10 microns width is formed in the masking layer ; 4 of silicon nitride. Thereafter the further mask-ing silicon oxide layer is removed and the portion P~B 32437 29.4.75 .
104~749 of the polycrystalline silicon layer 3 underlying the opening formed in the silicon nitride layer ls remov-ed. This exposes in the aperture an edge portion 5 of the polycrystalline layer 3. A boron diffusion step is now carried out into the layer 3, via the exposed edge 5, at a temperature of 1075C for 10 ' minutes, using a boron nitride source. The masking ; layer 4 of silicon nitride masks against direct dif-fusion of boron into directly underlying portions of the layer 3 and the silicon oxide layer 2 in the !j aperture masks against diffusion of boron into the ~,~ underlying portion of the silicon body 1. Boroh is ~ diffused into the layer 3 laterally under the silicon i nitride masking layer 4 to form in the polycrystalline layér 3 adjacent the edge of the aperture a relatively - low resistivity conductive region 6 in tha form of a diffused ~-strip portion 6 having a substantially - uniform line width of approximately 1 micron. The . , .
measured value of the sheet reSistance of the portion 6 is 100 ohms per square. The boundary between the p+-~ . .
portion 6 and the remaining portion of the layer 3 ; is considered as the location where the diffused boron concentrationis 10 3 times the value of the diffused ;~ boroff concentration at the surfaoe through which the - diffusion was effected.
After the boron diffusion step the remain-ing portion of the silicon nitride masking layer 4 is .
. - . .
., ,~ .
~ . .
29.4.75 ~ . _ . .. . _ , , removed by d~ssolving in hot phosphoric acid and then the polycrystalline, silicon layer 3, 6 is subjected to a sele~tlve etching treatment to remove the undiffuse*
, , portions 3 and thereby leave the relatively low resis-~ .
tivity diffused strip portion 6 of closed configura-tion situated adjacent the edge of the previously formed aperture 5. This is carried out by etching with a fluid consisting of 180 cc. of ethylene diamine, 30 gms. of pyrocatechol and 80 cc. of water. The etch-ing is carried out at a temperature approaching the .
boiling point of the etchant fluid and in the region of 110C.
:
The next 'step in the processing, is to remove , part only of the diffused strlp portion 6 of the poly-crystalline layer. This is carried out by first deposit-' ing a thin silicon oxide masking layer over the whole , surface including the strip portion 6. By means of a photomasking and etching step this silicon oxide mask-ing layer is removed except from the area of the strip portion 6 desired to be retained, The exposed parts of the strip portion 6 are then dissolved in a solution ' ' consisting of 50 cc. of concent~ated n'itric acid, ~; 20 cc. of water and 1 cc. of 40% hydrofluoric acid.
~; There remains a diffused strip part 7 of the poly-cry~talline silicon layer in the form of a linear portion of 1 micron width-and 20 microns length.
Figure l(e) shows the remaining strip part 7 having , .
.,:, . .~: ' ' PHB 32~137 29.4.75 .
: . . . .
10407gg the residual portion of the thin silicon oxide masking layer thereon. The strip 7 may form, for example, the gate electrode of an insulated gate field effect tran-sistor, It will be appreciated that the masking layer 4 used may be of a material other than silicon nitride, for example of silicon oxide.
Referring now to Figures 2(a) to 2(c), in ,: .
this embodiment the semiconductor substrate 1, sili-con oxide layer 2, polycrystaIIine silicon layer 3 and silicon nitride masking layer 4 are provided in the same manner as in the previous embodiment. An aperture is formed in the silicon nitride masking ., .
layer 4 without removing the underlying portion of the polycrystalline silicon layer 3 so that the re-sidual masking layer is therefore ofs~aller area than the polycrystalline layer on which it is present and adjacent the edge portion of the masking layer formed by the aperture therein the upper surface of the poly-crystalline silicon layer 3 is exposed. A phosphorus diffusion step is then carried out by diffusing phos-phorus, for 10 minutes at 1050C using a phosphorus - oxychloride source, into the exposed surface portion of the layer 3 such that lateral diffusion of phos-phorus occurs in the layer 3 under the masking layer 4 to form a relatively low resistivity n+-conductive region. Thereafter any residual oxide layer formed :~:
~ .
: , . .
.. ;: ' ' ' . .
. PHB 32437 - . 29.4.75 ~. ' , ' ,, , ' ' , .
.
::~ during the phosphorus diffusion step is removed in a suitable etchant and a boron diffusion step carried out under the same conditions as in the previous em-bodiment to diffuse boron into the exposed surface of the layer 3 in a higher concentration than~the pre-viously diffused phosphorus but to a lesser distance . laterally in the layer. Figure 2(b) shows the structurethus obtained with an n+ diffused region in the form . of a strip of substantially uniform width of 1 micron :. 10 extending under the edge of the masking layer 4 and adjoining a ~++ diffused region in the aperture, a ~-n junction 10 between the strip 8 and the outer-mo~t diffusion region 9 extending substantially in the dlrection of thickness ofthe layer 3 and below the masking layer 4. In this embodiment also, the boundary .; ' . .
: -- between the n -strip 8 and the undiffused portion of , the layer is considered as the location where the . ~ ; . diffused phosphorus concentration is 10 3 times the value a* the surface through which the diffusion was effected.
~he resldual portion of the sllicon nitride ' masking layer 4 is removed by dissolving in hot phosphoric acid and then the polycrystalline silicon layer is subjected to a selective etching trestment 2~ to remove only the. relatively narrow n -diffused - strip portion 8 and thereby form in the polycrystal-~ , . . .
~ . line silicon layer a strip-form aperture 11 of cLosed .
~' - .
.
_ 20 ::
29.4.75 104~749 configuration of 1 micron width, The etchant used comprises hydrofluoric.acid, nitric acid and acetic acid. - _ Referring now to Figures 3(a) to 3(c) there will be described in outline pa~t of the manufacture of a semiconductor device comprising an insulated gate field effect transistor by a method in accord-:. .
ance with the invention. On an n-type silicon sub-strate 12 of 4 ohm-cm. resistivity and 250 microns thickness there is thermally grown a relatively thick silicon oxide layer 13 of 1 micron thickness.
An aperture is formed in the thick oxide layer 13 ~, .
by a photomasking and etching step, the extent of this aperture being indicated by a broken line in - 15 Figure 3(a). A relatively thin silicon oxide layer - 14 of 1200 A thickness is thermally grown on the s~ilicon surface exposed in the aperture.
A polycrystalline silicon layer is deposit-~ ed over the whole upper surface of the body. A mask-; ~ 20 ing layer of silicon nitride is deposited over the - entire surface of the polycrystalline silicon layer 15 and a fùrther masking layer of silicon oxide de-posited on the silicon nitride layer~ By a photo-:: .
~ masking and etching step an aperture is formed in .~
- ~ 25 the upper silicon oxide masking layer and the portion of the silicon nitride masking layer 16 exposed by said aperture-is selectively removed together with the ... .
~ - - 21 . . :
29.4.75 underlying portion of the polycry'stalline silicon layer. Thereafter the remaining portion of the upper silicon oxide layer is removed. The polycrystalline silicon layer is thus defined as a plurality of dis-crete portions including the portion 15 shown in Fi-gures 3(a) and 3(b) and each covered with a portion of the silicon nitride masking' layer 16. The extent of the polycrystalline silicon layer portion 15 is ~, indicated in Figure 3(a) by a chain line.
A boron diffusion step is carried out as ' described with reference to Figure 1 to diffuse boron laterally into the polycrystalline silicon layer portion 15 via the exposed edges thereof.
This diffusion forms a +-strip 17 at the edge of the layer portion 15 and located below the silicon nitride masking layer 16. The ~ -strip 17 ~as a J width of approximately 1 micron.
' The remaining portions of the silicon nitride .
' masking layer, including the portion 16, are,removed ;~ 20 by dissolving in hot phosphoric acid. Thereafter the ~ polycrystalline silic,on layer is subjected to a selec-.~, , ,~ ~ tive etching treatment using the etchant as described - with reference to Figure 1 to remove theundiffused '~ portions of the polycrystalline silicon layer and ~` ~ 25 leave the ~+- diffused strip 17.
~' A further processing step may now be carried ~: .
;~" out to remove part of the ~+-strip 17, this comprising .. ~,. . , ~ .
, .', ' , , .
.~ . . . .
:'' ,. ~ . ~. . -~ '.'. ' , ' . .
29.4.75 1041)749 the deposition of a further masking layer, a photo-masking and etching stage to leave covered by the fur-ther masking layer only the portion of the strip 17_ it is de.sired to retain, an etching step to remove ~. 5 the exposed portion of the strip 17, and finally ; removal of the remaining portion of the further masking layer.
There remains, as shown in Figure 3(c) a linear strip 18 of p~-diffused polycrystalli.ne silicon -10 on the thin oxide layer 14. This forms the gate elec-trode of an insulated gate fie~d effec~ transistor, . ;,, -source and drain regions 19 and 20 respectively being formed by implanting boron ions in the semi-conductor body through the exposed parts of the thin oxide.layer 14 whilst using the masking effect of the gate electrode 18 to give a self registered structure. Thereafter electrical connection to the source and drain regions a~d to the gate electrode is made by any suitable conventionally employed . 20 method which involves etching contact windows, de-;~: position of a metallization layer and its subsequent definition by photomasking and etching techniques.
:: .
It will be appreciated -that this is a generalized . embodiment serving to illustrate the use of the method to form a gate electrode of narrow width in an insulated gate Pield effect transistor and when such a transistor forms part of an integrated circuit - "
29.4.75 then the further connection of the various regions of the transistor will have to be considered. In parti-cular the contacting of the strip gate may involve special measures to be adopted in the processing. This may be effected by locally providing the polycrystal-' line silicon in contact with the silicon surface where an implanted region is to be formed, or by overlapping the end of the gate with an applied metal contact layer at an area on the thick oxide layer, or by an extra diffusion step carried out prior to providing the ' silicon nitride masking layer and involving the dif-, fusion of boron into an edge portion'of the po,lycrystal-line silicon layer which will be continuous with the ,~ .
- gate strip when formed in said layer.
'` Referring now to Figures 4(a) and 4(b) a further embodimënt of the said first main form of the ~. - .
;~ , method will be described. The starting material and initially applied layers are exactly the same as in the embodiment dascribed with reference to Figure 1, ., .
; 20 namely the n-type silicon substrate 1, the silicon ' oxide masking layer 2, the high resistivity deposit-:~ .' , ' e,d polyorystalline silicon layer 3 and the silicon ,; nitride masking layer 4. By applying a further mask-.~, ing layer of silicon oxide and carrying out a photo-masking and etching step a portion of the silicon ~' nitride layer 4 is removed'by dissolving in hot phosphoric acid so that only'a central'portion of ~: , :'' ~ ' , _ 24 ,. .': ' ,,: . . .
..., ,.., ~, 29.4.75 ~, . . .
la4074s substantially rectangular configuration remains. The -portion of the high, resistivity polycrystalline sili-con layer 3 thus exposed is then removed by etching_with ', the nitric acid and hydrofluoric acid solution referred~ 5 ~ to in the embodiment described with reference to Fi-; gure 1. A boron diffusion step is then carried out to ' diffuse boron laterally into the edge of the portion of the high resistivity polycrystalline layer under the silicon nitride masking layer 4. The boron dif-fusion is effected at 1,050C for 20 minutes such that boron diffuses laterally under the silicon nitride layer 4 to a distance of 1 micron for a ' 10 3 reduction in ooncentration of diffused boron.
, Thereafter a further diffusion step is carried out 15 ' using-phosphorus, said diffusion being effected laterally via the edge of the portion of the poly-crystalline layer and previously having boron lateral-... .
' ' , ly diffused therein. The phosphorus is diffused at .. . . .
; 1,050C for 5 minutes using a phosphorus oxychloride ' 20 source. In this manner phosphorus is laterally dif-`-' fused at'a higher,concentration but at a smal,l , , ~ v distance in -t,he edge portions of the polcrystalline ,:
'' ~ ' , layer'. The silicon oxide layer 2 masks against :.i.' . , .
~;' introduction of boron or phosphorus into the portion ' ~ 25 - of the silicon body underlying the polycrystalline ;; ~ layer during said diffusions into the edge portions .~.~ . .
- of the polycrystalline l~yer. The outer n+-regions .,." ' ' ~, ...
. ~ , :,' . . ' .
- . .
,, , _ 25 ., ~
. . .
- . .
29.4.75 formed by the ph'osphorus diffusion form a ~-n junction with the inner ~-type region at a lateral distance of ' ' approximately 0.5 micron from the edges. These junctions extend substantially perpendicular to the plane of the main surface of the silicon oxide layer -~ ' 2 on the silicon body. This results in the definition of inner ~-type regions in the form of strips of 0.5 , micron width.
The remaining portion of the silicon nitride masking layer 4 is removed and the exposed polycrystal-line silicon layer is subjected to a select'ive etching treatment to leave only the p-type strips as shown in Figure 4(b). The etchant used consists of 180 cc. of ethylene diamine, 30 gms. of pyracatechol and 80 cc.
of wat'er. The p-type strips thus formed having a sub-' stantially constant width of 0.5 micron are such that :, , the edges of the strips are well defined and substan-~''' ; ' '
~ 104~)749 , .
form of the method to be described hereinafter the low resistivity conductive region havlng a substantially uniform line width is selectively removed to leave an aperture of relatively narrow wi.dth, said aperture being required in the further processing for the manu-- facture of a semiconductor device.
In some forms of the method, hereinafter referred to as first main forms, at an edge portion of the masking layer an edge of the po~ycrystalline ~ayer is exposed throughout the thickness of the poly.crystalline layer and diffusion of the doping element is effected laterally into the polycrystal-lile laye.r via the exposed edge portion to form a relatively low resistivity diffused strip portion of substantially uniform width.
: In one such first main form, subsequent to the diffusion process the masking layer is re-, . ~ moved and the polycrystalline layer is subjected to . . an etching treatment to selectively remove the un-diffused portions and thereby leave at said edge of ~ .
the polycrystalline layer the relatively low resis-. tivity diffus.ed strip portion. In some applications, .
~ including one to be described hereinafter, it may ~,., not be necessary to remove the undiff.used portions . and in fact not even necessary to remove the masking : .. . . .
`~ . layer.
In another first main form the diffusion .'': . . ' ~ - 6 , :
~ - lQ4V749 effected into the edge of the polycrystalline layer comprises first diffusing a doping element charac-teristic of ~ne conductivity type followed by diffus-inf a do'ping element characteristic of the opposite - ~ 5 conductivity type in a higher concentration but to a lesser distance laterally in the layer so that a ~-n junction extending s~bstantially in the direction of thickness of thé layer is formed between the outer-most diffused region characteristic of the opposite ' 10 conductivity type and th~e adjoining diffused region character~istic of the one conductivity type of sub-stantially uniform width and situated below the masking layer. Subsequent to this double diffusion process the masking layer may be removed and the polycrystalli~e layer subjected to an etching treat_ ment to selectively remove the outermost diffused `~ - region of the opposite conductivity type and the un-diffused portions of the layer and thereby leave ad-jacent said edge of the polycrystalline layer a rela-tively low resistivity diffused strip portion of the . ~ .
- one conductivity type and of substantially uniform ~; ~ width. In ~this manner it is possible to form a fine line of doped polycrystalline material of the one - condoctivity type having a well defined upper edge ~ 25 without discontinuities.
:~ . - .
In some other forms of the method, herein-after referred to as second main forms, the masking ., . PHB 32437 29.4.75 ' ' ' , ' .
layer is of smaller area than the polycrystalline layer on which it .is present so that.adjacent the edge portion of the masking lay~r the upper surface ofthe polycrystal-line layer is exposed, the diffusion process comprising first diffusing a doping element characteristic of one conductivity type into said exposed surface such that : lateral diffusion of the element occurs under the masking layer and then diffusing a doping element ., : . characteristic of the opposite conductivity type into said exposed surface in a higher concentrat~n - but to a lesser distance laterally in the layer so that a p-n junction extending substantially in the direction of thickness of the layer is formed under the masking layer between the outermost diffused 15 region of the opposite conductivity type and the ad-: . joining diffused region of the one conductivity type ~: ~ of substantially uniform width and extending under , the masking l.ayer. Subsequent to the double diffusion - . process the masking layer may be removed and the polycrystalline layer subjected to an etching treat_ . ment to selectively remove only the relatively narrow - . diffused region of the one conductivity type and ; thereby form in the polycrystaIline layer an aperture of relatively narrow and substantially uniform width.
This form of the method may be employed, for example, in the manufacture of a charge coupled device (CCD) - in which the insulated gate electrodes are formed ' . . .
. - 8 29.4.75 , '' ' ' ' .
:' , ..
from a layer of polycrystalline semiconductor material and apertures of the said relatively narrow and sub-stantially uniform width are formed in the layer to define the electrodes wlth a very close spacing.
One or more of the said first main forms of the method may be employed in the manufacture of ; a semiconductor device comprising at least one in-sulated gate field effect~transistor, the relatively low resistivity diffused strip portion of the poly-crystalline semiconductor layer forming at least part oP the gate electrode of the transistor. This method of forming the transistor may have significant advantages where it is desired to have a narrow chan-, nel region, that is a gate electrode in the form of ~ 15 a narrow strip, a~ will be described hereinafter in :,.~ , , : connection with one specific embodiment.
J.
~l In one form of such a method in which sub-.. .! : . .
sequènt to the diffusion process the masking layer - is removed and the polycrystalline layer is subjected to a selective etching treatment to remove the undif-fused portions of the polycrystalline layer, subse-quent to the selective etching at least parts of the source and drain regions of the transistor are formed -~ by impurity lntroduction into lhe semiconductor body at opposite sides of the diffused strip portion of the polycrystalline layer, said strip portion mask-ing against impurity introduction into the portion ~ ', .,, " ~ ' .
: _ g 29.4.75 104~)749 of the semicondu.ctor body lying below said strip portion.
In this self-registered method of forming the source and drain regions the said impurity introduction may be effected by ion implantation, for example, by im-planting ions through the insulating layer present on the semiconductor body surface on opposite sides of the said diffused strip portion of the polycrystal-line layer.
The semiconductor device manufactured by one of the said first main forms of the method may be an integrated circuit comprising a plurality of insulated gate field effect transistors having thei~ gate electrodes formed by doped portions of the poly-crystalline semiconductor layer, the said insulated : . 15 gate field effect transistor in which the diffused strip portion constitutes at least part of the gate : -. electrode being formed as a resistive load transis-tor and having the gate electrode connected to the ; drain region. In this manner a high load impedance may be obtained by using such a transistor because the provision of the gate electrode at least in part by the diffused strip portion of the polycrystal-. . ~
line layer enables a high w~' ratio to be obtained.
Such.an integrated circuit may comprise two of the transistors formed as resistive loads and having their gate electrodes connected to a com-` mon drain region, the gate electrodes of said two _ 10 : 29.4.75 . . .~
, . . .. .
104~)749 ~ transistors comprising laterally diffused strip - portions of the polycrystalline layer of substan-tially uniform wldths and situated at opposite edges of a single part of t~e polycrrstalline layer. When ,, in such an integrated circuit the semiconductor body is of silicon and the deposited polycrystalline layer is also of silicon, the method in accordance with the invention may be employed in such manner that the departure from conventionally employed "silicon gate"
processing is minimal and effectively may only involve ,.. . .
the addition of one non-critical masking stage as will .; be described hereina~ter in connection with a specific embodiment of such a method.
.Thus in the said circuit comprising the said ; 15` two load transistors the diffusion to form the gate electrode strip portions of the polycrystalline layer ~ ~ may be effected in the presence of a masking layer '': ~ ' ' ' ' locally present on said part of the polycrystalline layer, said diffusion being carried out simultaneous-ly with the diffusion to form at least part of the source and drain regions of the transistors and to , ~ : . . .
render more highly conductive other exposed portions of the polycrystalline layer, for example portions which are to constitute gate electrodes of other ` : :
transistors in the integrated circuit.
~ The said masking layer locally present on :- . . .
~-~ said part of the polycrystalline layer may comprise .: ... .
; ' , .
.....
.
.~ .
, , PHB 32437 29.4.75 .
~04~749 a residual part of a layer provided at the surface of the polycrystalline layer and employed for the previous definition of the polycrystalline layer into a plura-lity of discrete parts, for example a layer of silicon oxide or silicon nitride.
.. . The method may be employed in the manufacture of a semiconductor device in the form of an integrated . circuit in which at least one portion of the poly-crystalline semiconductor layer constitutes a conduc-tive track which crosses and i9 insulated from an un-. derlying diffused connection region in the semicon--1 ductor body, the opposite edge portions of the track : at the area of the crossing being converted into low resistivity diffused strip portions by the said - 15 lateral diffusion in the presence of a masking layer on the track at the area of the crossing.
~: . In this manner a compact crossing connection can be achieved and this may be incorporated in con-ventional ~silicon gate~ processing by the addition of a single non-critical mask alignment stage and ~ .
only one additional diffusion step.
In one form of such an integrated circuit ~ including a crossing Or t~is configuration the in-:: .
: tegrated circuit comprises a plurality of insulated gate field effect transistors having their gate elec-`~ trodes formed by doped portions of the polycrystalline , semiconductor layer, the method being employed such , PHB 32437 29.4.75 .. . . . .
. ~ ,, ~ . , -that the said diffusion is carried out to form at least part of the source and drain regions of transistors and to dope exposed up~er surface portions of the polycrystalline semiconductor layer. - -In one form of the method in which the lateral .
diffusion is employed to form low resistivity diffused strip portions of a conductive track, subsequent to ~' forming the low resistivity diffused strip portions ', , at the opposite edge portions of the track at the ~ 10 area of the crossing, the undiffused central portion ', of the track at the area of the crossing is selective~
~, ly removed and a further diffusion is carried out to '~, form at the area of the crossing a diffused surface "' ~ region in the semiconductor body in the f,orm of a ; 15 strip situated,intermediate the portions of the body ~ .. . . .
'~ above'which th,e low resistivity diffused strip ~: .
~, portions of the track are present, said diffused . . .
~, - surface region forming part of the diffused con- , :,............ :
nection region. In some embodiments this further ' Z0 diffusion step is also carried out to form at the area of the crossing diffused surface regions in the , .. . .
' ~ semiconductor body situated adjacent and extending :: . - .
'' inwardly below the said oppositç edges of the'track ', at which the low resistivity diffused strip portions . . .
have been formed, said diffused surface regions form-,~ ing parts of the diffused connection region. It is `-' ' not necessary that the last mentioned diffused surface :.. ,:, .
, - - 1~ , .
. ~, .
, Z9.4.75 .
- ~040749 regions shouid extend in contact with the intermediate-ly situated diffused strip region but only necessary that the spacing and the resistivity ~ the adjoining material of the body should be such that in operation the depletion layers associated ~th the junctions be-tween these regions and the adjoining material of the body meet to establish the continuity of the diffused connection region. Preferably the spacing and the re-sistivity are such that the depletion layers meet with no applied bias across the junctions.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which:
, Figures l(a) to 1(e) show in cross-section part of a semiconductor body and applied layérs dur-ing successive sbages in a first embodiment of the method in accordance with the invention;
` Figures 2(a) to 2(c) show in cross-section part of a semiconductor body and applied layers dur-ing successive stages in a second embodiment of the method in accordance with the invention;
Figures 3(a) and 3(b) show in plan view and in cross-section respectively part of a semi-conductor body and applied lay~rs during a stage in ~ 25 . the manufacture of a device comprising an insulated - gate field effect transistor by a method in accord-ance with the invention and Figure 3(c) shows in .
-29.4.75 .'' ~0407~9 cross-section said semiconductor body at a later.stage in the manufacture; .
,~ , Figures 4(a) and 4(b) show in cross-section ' part of a semiconductor body and applied layers during 5 various stages in a further embodiment of ~the method ~', . in accordance with the invention;
. , .
Figures 5(a) and 5(b) show in plan view and cross-section respectively part of the semicon-. ductor body and applied layers of a prior art "silicon gate" integrated circuit in which an insulat-: ed gate field effect transistor having its gate elec-,, .
,' , trode shorted to the drain region is used as & load .'~ ' impedance; ~ , Figure 6 is a circuit diagram showing part of a memor,y cell formed in a known integrated cir-.. - cuit, the memory cell including a cross-coupled pair ., J ~ . ~
.~ ~ of insulated gate field effect transistors each hav-' : - ing in series wi'th i,ts source a load impedance con-~ , . .
',, stituted by an insulated gate field effect t~ansistor having its gate electrode shorted to the drain region;
, Figure 7 shows in plan view part of a semi- .
.
;', conductor body in which the load transistors shown in .
.~ the circuit diagram of Figure 6 are present in in-. A ~ . . .
.' . . tegrated form and obtained by a method in accordance with the invention,;
Figures 8, 9 and 10 are cross-sectional .
views along the lines YIII - VIII, IX - IX and X - X
, , 29.4.75 104~749 respectively in Figure 7;
Figure 11.shows in plan view part of a semi-conductor body of a further integrated circuit compris-ing a plurality of insulated gate field effect transis-tors; and Figures 12 and 13 are cross~sectional views al~ng the lines XII - XII and XIII - XIII respective-ly in Figure 11.
Referring now to Figure 1 there will be described in general outline one illustrative embo-diment of the method in accordance with the invention.
On the surface o~ an n-type silicon substrate 1 of 250 microns thiokness and 4 ohm-cm. resistivity there is thermally grown a silicon oxide layer 2 of 0.1 micron thickness by any conventionally employed method. On the surface of the silicon oxide layer there is de-posited a layer of high resistivity polycrystalline silicon 3 of o.6 micron thickness, this layer being provided by any commonly used method. On the surface of the polycrystalline silicon lauer 3 there is de-posited a masking layer of silicon nitride 4 of 0.2 micron thickness. By first depositing a further mask-ing silicon oxide layer (not shown) and then carrying out a photomasking and etching process an aperture of 10 microns width is formed in the masking layer ; 4 of silicon nitride. Thereafter the further mask-ing silicon oxide layer is removed and the portion P~B 32437 29.4.75 .
104~749 of the polycrystalline silicon layer 3 underlying the opening formed in the silicon nitride layer ls remov-ed. This exposes in the aperture an edge portion 5 of the polycrystalline layer 3. A boron diffusion step is now carried out into the layer 3, via the exposed edge 5, at a temperature of 1075C for 10 ' minutes, using a boron nitride source. The masking ; layer 4 of silicon nitride masks against direct dif-fusion of boron into directly underlying portions of the layer 3 and the silicon oxide layer 2 in the !j aperture masks against diffusion of boron into the ~,~ underlying portion of the silicon body 1. Boroh is ~ diffused into the layer 3 laterally under the silicon i nitride masking layer 4 to form in the polycrystalline layér 3 adjacent the edge of the aperture a relatively - low resistivity conductive region 6 in tha form of a diffused ~-strip portion 6 having a substantially - uniform line width of approximately 1 micron. The . , .
measured value of the sheet reSistance of the portion 6 is 100 ohms per square. The boundary between the p+-~ . .
portion 6 and the remaining portion of the layer 3 ; is considered as the location where the diffused boron concentrationis 10 3 times the value of the diffused ;~ boroff concentration at the surfaoe through which the - diffusion was effected.
After the boron diffusion step the remain-ing portion of the silicon nitride masking layer 4 is .
. - . .
., ,~ .
~ . .
29.4.75 ~ . _ . .. . _ , , removed by d~ssolving in hot phosphoric acid and then the polycrystalline, silicon layer 3, 6 is subjected to a sele~tlve etching treatment to remove the undiffuse*
, , portions 3 and thereby leave the relatively low resis-~ .
tivity diffused strip portion 6 of closed configura-tion situated adjacent the edge of the previously formed aperture 5. This is carried out by etching with a fluid consisting of 180 cc. of ethylene diamine, 30 gms. of pyrocatechol and 80 cc. of water. The etch-ing is carried out at a temperature approaching the .
boiling point of the etchant fluid and in the region of 110C.
:
The next 'step in the processing, is to remove , part only of the diffused strlp portion 6 of the poly-crystalline layer. This is carried out by first deposit-' ing a thin silicon oxide masking layer over the whole , surface including the strip portion 6. By means of a photomasking and etching step this silicon oxide mask-ing layer is removed except from the area of the strip portion 6 desired to be retained, The exposed parts of the strip portion 6 are then dissolved in a solution ' ' consisting of 50 cc. of concent~ated n'itric acid, ~; 20 cc. of water and 1 cc. of 40% hydrofluoric acid.
~; There remains a diffused strip part 7 of the poly-cry~talline silicon layer in the form of a linear portion of 1 micron width-and 20 microns length.
Figure l(e) shows the remaining strip part 7 having , .
.,:, . .~: ' ' PHB 32~137 29.4.75 .
: . . . .
10407gg the residual portion of the thin silicon oxide masking layer thereon. The strip 7 may form, for example, the gate electrode of an insulated gate field effect tran-sistor, It will be appreciated that the masking layer 4 used may be of a material other than silicon nitride, for example of silicon oxide.
Referring now to Figures 2(a) to 2(c), in ,: .
this embodiment the semiconductor substrate 1, sili-con oxide layer 2, polycrystaIIine silicon layer 3 and silicon nitride masking layer 4 are provided in the same manner as in the previous embodiment. An aperture is formed in the silicon nitride masking ., .
layer 4 without removing the underlying portion of the polycrystalline silicon layer 3 so that the re-sidual masking layer is therefore ofs~aller area than the polycrystalline layer on which it is present and adjacent the edge portion of the masking layer formed by the aperture therein the upper surface of the poly-crystalline silicon layer 3 is exposed. A phosphorus diffusion step is then carried out by diffusing phos-phorus, for 10 minutes at 1050C using a phosphorus - oxychloride source, into the exposed surface portion of the layer 3 such that lateral diffusion of phos-phorus occurs in the layer 3 under the masking layer 4 to form a relatively low resistivity n+-conductive region. Thereafter any residual oxide layer formed :~:
~ .
: , . .
.. ;: ' ' ' . .
. PHB 32437 - . 29.4.75 ~. ' , ' ,, , ' ' , .
.
::~ during the phosphorus diffusion step is removed in a suitable etchant and a boron diffusion step carried out under the same conditions as in the previous em-bodiment to diffuse boron into the exposed surface of the layer 3 in a higher concentration than~the pre-viously diffused phosphorus but to a lesser distance . laterally in the layer. Figure 2(b) shows the structurethus obtained with an n+ diffused region in the form . of a strip of substantially uniform width of 1 micron :. 10 extending under the edge of the masking layer 4 and adjoining a ~++ diffused region in the aperture, a ~-n junction 10 between the strip 8 and the outer-mo~t diffusion region 9 extending substantially in the dlrection of thickness ofthe layer 3 and below the masking layer 4. In this embodiment also, the boundary .; ' . .
: -- between the n -strip 8 and the undiffused portion of , the layer is considered as the location where the . ~ ; . diffused phosphorus concentration is 10 3 times the value a* the surface through which the diffusion was effected.
~he resldual portion of the sllicon nitride ' masking layer 4 is removed by dissolving in hot phosphoric acid and then the polycrystalline silicon layer is subjected to a selective etching trestment 2~ to remove only the. relatively narrow n -diffused - strip portion 8 and thereby form in the polycrystal-~ , . . .
~ . line silicon layer a strip-form aperture 11 of cLosed .
~' - .
.
_ 20 ::
29.4.75 104~749 configuration of 1 micron width, The etchant used comprises hydrofluoric.acid, nitric acid and acetic acid. - _ Referring now to Figures 3(a) to 3(c) there will be described in outline pa~t of the manufacture of a semiconductor device comprising an insulated gate field effect transistor by a method in accord-:. .
ance with the invention. On an n-type silicon sub-strate 12 of 4 ohm-cm. resistivity and 250 microns thickness there is thermally grown a relatively thick silicon oxide layer 13 of 1 micron thickness.
An aperture is formed in the thick oxide layer 13 ~, .
by a photomasking and etching step, the extent of this aperture being indicated by a broken line in - 15 Figure 3(a). A relatively thin silicon oxide layer - 14 of 1200 A thickness is thermally grown on the s~ilicon surface exposed in the aperture.
A polycrystalline silicon layer is deposit-~ ed over the whole upper surface of the body. A mask-; ~ 20 ing layer of silicon nitride is deposited over the - entire surface of the polycrystalline silicon layer 15 and a fùrther masking layer of silicon oxide de-posited on the silicon nitride layer~ By a photo-:: .
~ masking and etching step an aperture is formed in .~
- ~ 25 the upper silicon oxide masking layer and the portion of the silicon nitride masking layer 16 exposed by said aperture-is selectively removed together with the ... .
~ - - 21 . . :
29.4.75 underlying portion of the polycry'stalline silicon layer. Thereafter the remaining portion of the upper silicon oxide layer is removed. The polycrystalline silicon layer is thus defined as a plurality of dis-crete portions including the portion 15 shown in Fi-gures 3(a) and 3(b) and each covered with a portion of the silicon nitride masking' layer 16. The extent of the polycrystalline silicon layer portion 15 is ~, indicated in Figure 3(a) by a chain line.
A boron diffusion step is carried out as ' described with reference to Figure 1 to diffuse boron laterally into the polycrystalline silicon layer portion 15 via the exposed edges thereof.
This diffusion forms a +-strip 17 at the edge of the layer portion 15 and located below the silicon nitride masking layer 16. The ~ -strip 17 ~as a J width of approximately 1 micron.
' The remaining portions of the silicon nitride .
' masking layer, including the portion 16, are,removed ;~ 20 by dissolving in hot phosphoric acid. Thereafter the ~ polycrystalline silic,on layer is subjected to a selec-.~, , ,~ ~ tive etching treatment using the etchant as described - with reference to Figure 1 to remove theundiffused '~ portions of the polycrystalline silicon layer and ~` ~ 25 leave the ~+- diffused strip 17.
~' A further processing step may now be carried ~: .
;~" out to remove part of the ~+-strip 17, this comprising .. ~,. . , ~ .
, .', ' , , .
.~ . . . .
:'' ,. ~ . ~. . -~ '.'. ' , ' . .
29.4.75 1041)749 the deposition of a further masking layer, a photo-masking and etching stage to leave covered by the fur-ther masking layer only the portion of the strip 17_ it is de.sired to retain, an etching step to remove ~. 5 the exposed portion of the strip 17, and finally ; removal of the remaining portion of the further masking layer.
There remains, as shown in Figure 3(c) a linear strip 18 of p~-diffused polycrystalli.ne silicon -10 on the thin oxide layer 14. This forms the gate elec-trode of an insulated gate fie~d effec~ transistor, . ;,, -source and drain regions 19 and 20 respectively being formed by implanting boron ions in the semi-conductor body through the exposed parts of the thin oxide.layer 14 whilst using the masking effect of the gate electrode 18 to give a self registered structure. Thereafter electrical connection to the source and drain regions a~d to the gate electrode is made by any suitable conventionally employed . 20 method which involves etching contact windows, de-;~: position of a metallization layer and its subsequent definition by photomasking and etching techniques.
:: .
It will be appreciated -that this is a generalized . embodiment serving to illustrate the use of the method to form a gate electrode of narrow width in an insulated gate Pield effect transistor and when such a transistor forms part of an integrated circuit - "
29.4.75 then the further connection of the various regions of the transistor will have to be considered. In parti-cular the contacting of the strip gate may involve special measures to be adopted in the processing. This may be effected by locally providing the polycrystal-' line silicon in contact with the silicon surface where an implanted region is to be formed, or by overlapping the end of the gate with an applied metal contact layer at an area on the thick oxide layer, or by an extra diffusion step carried out prior to providing the ' silicon nitride masking layer and involving the dif-, fusion of boron into an edge portion'of the po,lycrystal-line silicon layer which will be continuous with the ,~ .
- gate strip when formed in said layer.
'` Referring now to Figures 4(a) and 4(b) a further embodimënt of the said first main form of the ~. - .
;~ , method will be described. The starting material and initially applied layers are exactly the same as in the embodiment dascribed with reference to Figure 1, ., .
; 20 namely the n-type silicon substrate 1, the silicon ' oxide masking layer 2, the high resistivity deposit-:~ .' , ' e,d polyorystalline silicon layer 3 and the silicon ,; nitride masking layer 4. By applying a further mask-.~, ing layer of silicon oxide and carrying out a photo-masking and etching step a portion of the silicon ~' nitride layer 4 is removed'by dissolving in hot phosphoric acid so that only'a central'portion of ~: , :'' ~ ' , _ 24 ,. .': ' ,,: . . .
..., ,.., ~, 29.4.75 ~, . . .
la4074s substantially rectangular configuration remains. The -portion of the high, resistivity polycrystalline sili-con layer 3 thus exposed is then removed by etching_with ', the nitric acid and hydrofluoric acid solution referred~ 5 ~ to in the embodiment described with reference to Fi-; gure 1. A boron diffusion step is then carried out to ' diffuse boron laterally into the edge of the portion of the high resistivity polycrystalline layer under the silicon nitride masking layer 4. The boron dif-fusion is effected at 1,050C for 20 minutes such that boron diffuses laterally under the silicon nitride layer 4 to a distance of 1 micron for a ' 10 3 reduction in ooncentration of diffused boron.
, Thereafter a further diffusion step is carried out 15 ' using-phosphorus, said diffusion being effected laterally via the edge of the portion of the poly-crystalline layer and previously having boron lateral-... .
' ' , ly diffused therein. The phosphorus is diffused at .. . . .
; 1,050C for 5 minutes using a phosphorus oxychloride ' 20 source. In this manner phosphorus is laterally dif-`-' fused at'a higher,concentration but at a smal,l , , ~ v distance in -t,he edge portions of the polcrystalline ,:
'' ~ ' , layer'. The silicon oxide layer 2 masks against :.i.' . , .
~;' introduction of boron or phosphorus into the portion ' ~ 25 - of the silicon body underlying the polycrystalline ;; ~ layer during said diffusions into the edge portions .~.~ . .
- of the polycrystalline l~yer. The outer n+-regions .,." ' ' ~, ...
. ~ , :,' . . ' .
- . .
,, , _ 25 ., ~
. . .
- . .
29.4.75 formed by the ph'osphorus diffusion form a ~-n junction with the inner ~-type region at a lateral distance of ' ' approximately 0.5 micron from the edges. These junctions extend substantially perpendicular to the plane of the main surface of the silicon oxide layer -~ ' 2 on the silicon body. This results in the definition of inner ~-type regions in the form of strips of 0.5 , micron width.
The remaining portion of the silicon nitride masking layer 4 is removed and the exposed polycrystal-line silicon layer is subjected to a select'ive etching treatment to leave only the p-type strips as shown in Figure 4(b). The etchant used consists of 180 cc. of ethylene diamine, 30 gms. of pyracatechol and 80 cc.
of wat'er. The p-type strips thus formed having a sub-' stantially constant width of 0.5 micron are such that :, , the edges of the strips are well defined and substan-~''' ; ' '
3 tially free of irregularities, The ~-type strips shown i' , . , ,~ in the section of Figure 4(b) actually form part of ~ 20 a closed single strip located on the silicon oxide ,;',', layer 2 at an area corresponding to the area of p0ri-' phery of the portion of the polycrystalline silicon ,,,~ layer remaining masked by the silicon nitride layer ~,' after the init'ial removal of part of the silicon ~..... , ~ . 25 nitride layer 4 and underlying polycrystalline si-: .
i licon layer 3. If de~sired further treatments may be ' carried out to selectively remove at least a portion :.~ ' . ' . '` - .
~ ' ' ' - 26 _' , PI~B 32437 29.~.75 of this strip.
Referring to Figures 5(a) and 5(b) there will now be described a prior art form of "silicon gate"
integrated circuit in which a load impedance connect-ed to one insulated gate field effect transistor is constituted by-a second insulated gate field effect transistor having the gate electrode shorted to the drain region. For the sake of clarity of illustration only that part of the circuit where the second insulat-10 ~ ed gate field effect transistor is present is shown in Figures 5(a) and 5(b) and these Figures show this part at a stage in the manufacture prior to providing a contact pattern. The integrated circuit comprises a silicon substrate 31 having thereon an insulating layer-of silicon oxide comprising a relatively thick ; , portion 32 and a relatively thin portion ~3. In Figure 5(a) the boundary between the thick oxide 32 and the thin oxide 33 whhch c;orresponds to the location of ; an aperture initially formed in the thick oxide 32 prior to providing therein the thin oxide 33 is shown in a broken line. A continuous line 34 of dots in Figure 5(a) indicates the area over which the thin oxide 32 has been removed where lying within the ; boundary of said line 34 using a non-critical mask alignment stage. This local removal of the thin oxide layer has been followed by the deposition of a high resistlvity polycrystalline silicon layer over the . . .
.
.. .. . . .
29.4.75 .
whole surface and its subsequent definition into a plurality of discre~te portions. One such portion is the portion 35 which~constitutes the gate electrode---of the transistor. It is apparent from Figure 5(b) that the gate electrode 35 extends in contact with ; the silicon body surface where the thin oxide layer 33 was locally removed prior to the deposition of the polycrystalline siiicon layer. The transistDr comprises .
; p -diffused source and drain regions 36 and 37 respec-tively. These have been formed by diffusion of boron into portions of the silicon body sur~ace exposed by removing the parts of the thin oxide layer 33 not ',~ covered by the discrete portions of the polycrystal-~, , line silicon layer subsequent to the definition of said ~, 15 discrete portions. During this diffusion the gate elec-., .
~ ~ trode 35 is doped with the boron but the diffusion of .;:,~ . .
'''!" boron does not occur into the underlying channel region ~3~ of the transistor. It will'be apparent from Figure 5(b) that where th~ gate electrode 35 extends in contact s ~ 20 with the silicon body surface the diffusion of boron ; .
at this location in the body which has occurred via ... . . .
;, , this portion of the polycrystalline silicon layer .. .. . . . . . .
extends to a lesser depth in the body. However this part of the drain regi-on 37 is continuous with the ad-; 25 joining deeper diffused ~ -portions of the drain region :.............. .
~`- beyond the thus doped polycrystalline silicon layer , portion 35. Thus in this transistor the gate electrode .~ . ' ' , .
:. . .
- 28 _ -' '- P~B 32ll37 29.4.75 - 1040'749 35 is shorted to the drain region 37. It will be ap-: parent that to obtain such a r'esistive load transistor , with a high value resistance, then for a fixed resis-tivity of the channel region it is.necessary to have a large ratio of channel length 1 to channel width w and hitherto the problem has been that there is a limit on value to which w can be reduced and hence this has necessitated a very large channel length ~ to obtain the desired ratio for providing.a high value ,resistance. -, Figure 6 shows a circuit diagram of a memory '; cell part of an integrated circuit comprising a plura-~ lity of insulated gate field effect transistors. A
cross-coupled pair of transistors T1 and T2 have load , 15 impedances in series with the sources and respective-; ' ly constituted by transistors T3 and T4. The transis-" tors T3 and T4 having a common drain region have their . gate electrodes connected together and shorted to the common drain region. An integrated circuit test pat-' 20 tern form of that portion of the circuit shown in ' Figure 6 within the broken line 39 will be described, "' ' , w'ith reference to Figures 7 to 10, together with a ' . method of manufacturing such an integrated circuit ,' in "silicon gate" form by a method in accordance :; , .
'~ 25 . with the invention.
In Fig~re 7 the broken line, the continuows ' line of dots and the chain line have the same notation .
.
29.4.75 as in the structure shown in Figure 5(a). Thus the part of the integrated circuit shown comprises an n-type silicon substrate 51 of 4 ohm-cm. resistivity and 27-5 microns t~;ickness having thereon a relatively thick silicon oxide layer part 52 of 1.0 micron thickness and a relatively thin silicon oxide layer part 53 of 1200 A thickness. The continuous line of dots 54 in-dicates the area o~er which the thin oxide layer 53 was locally removed by etching following a masking stage which involved a non-critical mask alignment.
A discrete portion 55 of a deposited layer of high resistivity polycrystalline silicon is present and the boundary of said portion is indicated by a chain line in Figure 7. The inclined hatching in Figure 7 indicates the regions where boron has been diffused.
The closely spaced inclined hatching lines within the broken line indicating the boundary of the thick oxide , layer 52 indicate ~+-diffused surface regions formed ., by diffusion in the silicon body 51 at areas where the thin oxide layer 53 has been removed. These include the source regions 57 and 58 of the transistors T3 ` and T4 respectively and the common drain region 59 .: , of these transistors. The gate electrodes of these transistor;s are formed by laterally diffused low-resistivity strip portions 61 and 62 respectively at opposite edges of the high resistivity polycrystal-line silicon layer portion 55.
.
' , , PHB 32437 ' 29.4.75 , . . . . . .
~, The upper surface of the integrated device ls covered with a deposited layer 63 of silicon oxide and within this layer apertu~es 64, 65 and 66 are pre-sent via which are respectively contacted the common drain region 59 of tlle transistors T3 and T4, the source region 57 of the transistor T3 and the source ' . ' region 58 of the transistor T4. It will be appreciat-' ed that the part of the integrated circuit shown in - plan view in Figure 7 constitutes a tes,t pattern and .~ . .
"~ 10 therefore contact apertures 64, 65 and 66 are provided.
' In a full integrated oircuit the difference resides in , i : -,~ ' that no such separate apertures are present because the ,j: . .
3~ diffused regions 57 and 58 concerned form part of ,,~ other circuit elements, viz the drain regions of~the , 15 cross-coupled pair of transistors T1 and T2 in the '~ memory cell shown in Figure 6, and the diffused re-' - gion 59 will form an inte~connection to other memory ,,J: ,: , '`"''~ '~ cells.
~, In the manufacture of the integrated device "~,; 20 shown in Figures 7 to 10, subsequent to the deposition of the polycrystalline silicon layer on the whole upper surface of the body a masking layer of silicon oxide is applied to the whole surface of the poly-crystall~ine-silicon layer. Portions of this masking '- 25 , layer ære then selectively removed together with underlying portions of the polycrystalline silicon - layer so that there remain a plurality of discrete ' _ 31 .
.
,, , , . PHB 32437 29.4.75 - . :
polycrystalline silioon portions each having its sur-face covered by-the~masking layer material of silicon oxide. This corresponds to the normal "silicon gate'~
processing and in such a pr~cess the said masking layer of silicon oxide is removed by etching in the next stage of the processing together with the portions of the thin oxide layer 53 exposed upon the selective removal of the polycrystalline silicon. The manufacs ture of the integrated device shown in Figures 7 to 10 differs from the normal "silicon gate" processing t at this stage in that prior to the said etching an additional masking of the silicon oxide layer is `i carried out using photoresist which is selectively :
exposed and developed so that over a rectangular area 68 indicated ~y the continuous line of crosses an ad-ditional masking layer of photoresist is provided.
.: . .
` Thereafter the said etching of the exposed silicon ~ ,.. .
oxide masking layer on the polycrystalline sllicon :, :
layer together with the etching of the exposed por-tions of thin ox1de layer 53 is carried out. At this stage the part of the polycrystalline layer portion 55 lylng within the rectangle 6~ thus has layers of silicon oxide and photoresist thereon. The residual portion of the photore-sist layer is now removed to leave a silicon oxide layer portion 71 on that part of the polycrystalline silicon layer portion 55 situated within the area-of the rectangle denoted .
: ` ~
- , . - PHB.32437 ~ 29.4.75.
by a line of'crosses.
The next stage in t~e processing corresponds with the normal "silicon gate" processlng in that a .' boron diffusion step is car~ied out. The difference ,,I, 5 arises, however, that for the transistors T3 and T4 ', the boron diffusion into the polycrystalline siliconto render the gate electrode portions more hlghly ~ conductive is a lateral diffusion under the silicon 'l ' ' , -oxide masking portion 71 and via the edge portions of , 10 ,the layer part 55. This results in narrow strip ' ' ' portions 61 and 62 on opposite sides of the high ' resistivity polycrystalline silicon portion 55, said ... . .
. strip portions being of 1 micron width and 30 microns ;'I , length and shown in Figures 7, 8 and 9 in crossed hatchi'hg lines. The boron.diffusion is also effect-ed into exposed portions of the polycrystalline si-- licon layer portion at the'other.two opposite ends "~, . . .
'. Or the,polycrystalline silicon layer portion 55 l . situated beyond the silicon oxide masking 71 within - ~ . 20 ' the area of the rectangle 68. The boron is also dif-. .
fused into exposed'portions of the silicon body sur-:: , . . .
~: fiace to form the source'and drain regions of the , transistors T3 and T4. Also boron diffusion is effect-' ed into the'exposed portion 69 of the polycrystalline ' 25 ' . layer~which is in direct contact with the surface of the silicon body portion within the rectangular area 54 where the thin oxide was Locally removed before - ~ ' .
29.4.75 .
the deposition of the pulycrystalline silicon layer.
This so called 'CS' (for contact silicon) contact yields the desired connection between the gate elec-trodes 61, 62 and the common drain region 59.
In this manner the laterally diffused strips 61 and 62 form gate electrodes of the transistors T3 and T4 and due to their narrow width of 1 micron and the self-regi~tration of the source a~d drain regions ~. e the channels of these transistors have an w- ratio of ; 10 approximately 30. This yields load transistors having a high series resistance of the order of 1.0 x 10 ohms with a voltage of 8 volts on the gates and com-mon drain relative to the sources.
, In this embodiment the gate electrodes formed by the laterally diffused strips 61 and 62 are joined by the remaining undiffused centre portion of the high ` resistivity polycrystalline layer portion 55. In some instances this remaining connection between the gate electrodes may be undesirable because of the diffi-culty in obtaining reproducibly a sufficiently high ; res~stlvity of the polycrystalline silicon layer in-termediate the strips and therefore a consequent .
lack of control of the effective width of the gate - electrode strips 61 and 62. Therefore in such instances :: . .
the processi~g may be suitably modified to enable the removal of the undiffused centre portion. One such adaptation of the pFeviously described process will ," , ' ' ' '' ' . .
- 34 ~
.
P~B 32ll37 . 29.~.75 now be given. In this adaptation the deviation starts with the definition of the high resistivity polycrystal-.~. .
line silicon layer into a plurality of discrete portions.
Thus, subsequent to the deposition of the high resis-tivity polycrystalline silicon layer a silicon nitride layer Of t 1 micron thickness is deposited on the . entire upper surface of the polycrystalline silicon , layer follo~ed by the deposition of a silicon oxide masking layer of 0.2 micron thickness. By a photo~
masking and etching step the upper silicon oxide .:; , , masking layer is removed according to the same mask_ ,, ing pattern as used for the definition of the poly-crystalline silicon layer into a plurality of discrete portions in the unmodified processing. The portions of "', 15 the silicon nitride layer thus exposed are then re-:!, ' moved. Thereafter all the residual portions of the : . . .
upper silicon oxide masking layer present on the re-maining silicon nitride layer portions are removed.
:,: ::~
This is followed by the removal by etching of the Z0 portions Or the polycrystalline silicon layer ex-posed where the silicon nitride layer has been re-- moved. Thus at this stage of *he processing at which the polycrystalline silicon layer has been defined as a plurali-ty of discrete portions the device is as in the normal processing with the exception that each discrete portion of the polycrystalline layer - has a silicoln nitride layer thereon instead of a ' - 3~ -.
,. .. .
.
.
r~`. :
~ .
29.4.75 .
~ 104~749 .~
- silicon oxide layer thereon. These silicon ni*ride layer portions are later selectively removed by a conventional .
plasma etching method. However prior to this plasma etching a further photomasking process is carried out, '~'' 5 using a non-critical mask alignment stage, to leave a ~ .. ! .
, , layer of photoresist on that portion of the upper sur-'' faces of the various layers within the rectangular ,' area 68 defined by the line of crosses in Figure 7.
', The plasma étching is then oarried out to remove the 'I 10 remaining exposed silicon nitride layer parts. ~th , . .
the additional photoresist layer still in place the thin oxide layer 53 is now etched' away in those areas ,.; .
'~ , where it has been exposed on account of the previous ', ' removal of the overlying polycrystalline silicon ' layer. Thu,s where bhe thin oxide layer 53 is present ~,~ withih the rectangular area 68 it is protected by the photoresist layer and therefore remains present during said etching. Following this the photoresist is removed and the boron diffusion step as described .,. ~ . . . .
, 20 in the previous embodiment is carried out to form the ~'~ ' low resistivity gaté electrode strips 61, 62, the source and d,rain electrode regions of the transis-' tors and to render more hi~hly conductive the exposed '~ ;, , upper, surface portlons of the polycrystalline silicon layer. This differs from the diffu.sion as described in the previous embodiment only in that the masking on the polycrystalline silicon portion 55 within the , , " 3~ , 29.4.75 ~ 1040749 area 68 is of silicon nitride instead of silicon oxide.
Subsequent to the boron diffusion the residual portion of the silicon nitride layer on the polyorystal-line silicon portion 55 is removed and thereafter a 5 selective etching treatment is carried out to remove the undiffused centre portion of the polycrystalline silieon portion 55 lying between the low-resistivity diffused strips 61 and 62.
The subsequent processing both for the first deseribed embodiment of the method for forming the in-. . tegrated cireuit of which part is shown in Figures 7 to 9 and for the modified, seeond deseribed embodiment of the method involves the deposition of a silicon oxide glass passivation layer 63, the opening of eontact apertures, the deposition of an interconnec-tion metal layer, the definition of said layer, -. mounting and encapsulation in accordance with con-ventionally employed processing.
; Referring now to Figures 11 to 13 a further embodiment of the method in accordance with the inven-tion will be described, In this embodiment the semi-conductor device is an integrated circuit comprising a plurality of insulated gate field effect transis-tors having ga.te electrodes formed of doped poly-crystalline silicon, the circuit being formed by a similar process as the sai~ unmodified form described with reference to Figures 7 to 10. In the embodiment - ~} _ /~ -' _ .
;;1 104~)749 now to be described the method as was employed to form the gate electrode~strips 61 and 62 by lateral diffusion in the polycrystalline silicon iayer portion in the said unmodified process, is now employed to form a crossing connection in a simple manner with the addition of only one non-critical mask alignment stage and a diffusion step. The crossing connection is between a doped poly-.~ , .
crystalline layer portion 73 and a diffused connection region comprising ~+-regions 74 and 75 at opposite ., .
sides of the'area at wh~ch the crossing occurs and further ~-type regions 79, 80 and 81. The ~ -regions 74 and 75 are formed as diffused regions bounded by the thick oxide layer 52 and these regions may be contiguous with main electrode regions of two insulat-ed gate field-effect transistors. The polycrystalline silicon layer portion 73 is in the form of a track of 10 microns width which lies on the thicker oxide ~ layer 52 with the exception of the area of the cros-,~".~ , , sing where it lies on the thinner oxide layer 53.
~, ~ 20 Within the rectangular area 76 indicated by the ~; line of crosses the polycrystalline silicon layer portion forming part of the track 73 has been left covered with a masking layer of silicon oxide on its . ': ' surface at a stage of~the processing just prior to ~- 25 the boron diffusion. This is achieved with a non-~ ,~
critical mask alignment stage. Furthermore at the opposite edges of the track the thin oxide layer 53 ,.
'.'~ , . .
- _ ~ _ .`: ' ~
, ~ , , ' PHB 32~l37 29.4.75 ~: 1040749 remains within the rectangular area 76 at this stage of the processing. The boron diffusion is carried out as - in the previously described embodiments to laterally ~ diffuse boron below the silicon oxide masking layer ::
on the traok 73 within the area 76 and form conductive strip portions 77 and 78 each of 15 microns in length :,............................................... .
and each of 1 micron width at the opposite edges of the ; track. The boron diffusion is also effected to render ~ more highly conductive the exposed upper surface ,~ 10 portions of the track 73 situated on the thick oxide layer 52 beyond the rectangular area 76. Furthermore, as the silicon surface is exposed where the thin oxide layer 53 has been removed (with the exception of within the rectangular area 76) boron is diffused in these areas to form the ~+-regions including the regions 74 and 75 which constitute parts of the connection region.
The next step in the processing is to remove the remaining portion of the silicon oxide masking layer present on the track 73 within the rectangular area 76 and to remove the portions of the thin oxide ~;~ layer 53 on opposite sides of the track 73 also with-~ in the rectangular area 76. The undiffused portion of the polycrystalline silicon track 73 between the dif-fused strip portions 77 and 78 is then removed selec-tively using a preferential etching treatment. A fur-ther boron diff`usion step is then carried out to form ~ ' , ' , .
.~; , .`_ ~ _ .
. ..
.~f ~ HB 32l~37 ~ 29.4.75 : ., .
1040~49 diffused surface regions 79 and ~0 adjacent the opposite . sides of the track where the thin oxide layer 52 has been removed. This second diffusion is also carried out to diffuse boron through the thin oxide layer 53 -5 where exposed br the selective removal of the undiffused : polycrystalline silicon track 73 and to form a p-type : surface region 81 having on its opposite sides the ~-type regions 79 and 80. ~ue to the lateral diffusion of boron in the silicon body when forming the regions 79, 80 and 81, the outer regions 79 and 80 are each spaced from the region 81 by approximately 0.5 micron.
These rrgions 79, 80 and 81 constitute parts of a ~-type diffused connection region including and extend-ing between the p -regions 74 and 75. With an n-type substrate 51 of 4 ohm-cm. resistivity the spacing (0.5 micron) of the region~ 81 from the regions 79 and , 80 is sufficiently small that the junction depletion . , ~ .
; layers where they adjoin will meet and thus complete ; the connection even when there is no applied bias across the junctions between the substrate 51 and the regions 79, 80 and 81.
; . Thus in this manner a simple crossing is . achieved between a polycrystalline silicon track 73 and an underlying diffused connection region of which , . . . .
~ 25 the p+-regions 74 and 75 form the opposite ends, be-`~ cause a) the low resistivity laterally diffused strip ~ portions 77 and 78 complete the conductive path in the ,..
.; , . .
i licon layer 3. If de~sired further treatments may be ' carried out to selectively remove at least a portion :.~ ' . ' . '` - .
~ ' ' ' - 26 _' , PI~B 32437 29.~.75 of this strip.
Referring to Figures 5(a) and 5(b) there will now be described a prior art form of "silicon gate"
integrated circuit in which a load impedance connect-ed to one insulated gate field effect transistor is constituted by-a second insulated gate field effect transistor having the gate electrode shorted to the drain region. For the sake of clarity of illustration only that part of the circuit where the second insulat-10 ~ ed gate field effect transistor is present is shown in Figures 5(a) and 5(b) and these Figures show this part at a stage in the manufacture prior to providing a contact pattern. The integrated circuit comprises a silicon substrate 31 having thereon an insulating layer-of silicon oxide comprising a relatively thick ; , portion 32 and a relatively thin portion ~3. In Figure 5(a) the boundary between the thick oxide 32 and the thin oxide 33 whhch c;orresponds to the location of ; an aperture initially formed in the thick oxide 32 prior to providing therein the thin oxide 33 is shown in a broken line. A continuous line 34 of dots in Figure 5(a) indicates the area over which the thin oxide 32 has been removed where lying within the ; boundary of said line 34 using a non-critical mask alignment stage. This local removal of the thin oxide layer has been followed by the deposition of a high resistlvity polycrystalline silicon layer over the . . .
.
.. .. . . .
29.4.75 .
whole surface and its subsequent definition into a plurality of discre~te portions. One such portion is the portion 35 which~constitutes the gate electrode---of the transistor. It is apparent from Figure 5(b) that the gate electrode 35 extends in contact with ; the silicon body surface where the thin oxide layer 33 was locally removed prior to the deposition of the polycrystalline siiicon layer. The transistDr comprises .
; p -diffused source and drain regions 36 and 37 respec-tively. These have been formed by diffusion of boron into portions of the silicon body sur~ace exposed by removing the parts of the thin oxide layer 33 not ',~ covered by the discrete portions of the polycrystal-~, , line silicon layer subsequent to the definition of said ~, 15 discrete portions. During this diffusion the gate elec-., .
~ ~ trode 35 is doped with the boron but the diffusion of .;:,~ . .
'''!" boron does not occur into the underlying channel region ~3~ of the transistor. It will'be apparent from Figure 5(b) that where th~ gate electrode 35 extends in contact s ~ 20 with the silicon body surface the diffusion of boron ; .
at this location in the body which has occurred via ... . . .
;, , this portion of the polycrystalline silicon layer .. .. . . . . . .
extends to a lesser depth in the body. However this part of the drain regi-on 37 is continuous with the ad-; 25 joining deeper diffused ~ -portions of the drain region :.............. .
~`- beyond the thus doped polycrystalline silicon layer , portion 35. Thus in this transistor the gate electrode .~ . ' ' , .
:. . .
- 28 _ -' '- P~B 32ll37 29.4.75 - 1040'749 35 is shorted to the drain region 37. It will be ap-: parent that to obtain such a r'esistive load transistor , with a high value resistance, then for a fixed resis-tivity of the channel region it is.necessary to have a large ratio of channel length 1 to channel width w and hitherto the problem has been that there is a limit on value to which w can be reduced and hence this has necessitated a very large channel length ~ to obtain the desired ratio for providing.a high value ,resistance. -, Figure 6 shows a circuit diagram of a memory '; cell part of an integrated circuit comprising a plura-~ lity of insulated gate field effect transistors. A
cross-coupled pair of transistors T1 and T2 have load , 15 impedances in series with the sources and respective-; ' ly constituted by transistors T3 and T4. The transis-" tors T3 and T4 having a common drain region have their . gate electrodes connected together and shorted to the common drain region. An integrated circuit test pat-' 20 tern form of that portion of the circuit shown in ' Figure 6 within the broken line 39 will be described, "' ' , w'ith reference to Figures 7 to 10, together with a ' . method of manufacturing such an integrated circuit ,' in "silicon gate" form by a method in accordance :; , .
'~ 25 . with the invention.
In Fig~re 7 the broken line, the continuows ' line of dots and the chain line have the same notation .
.
29.4.75 as in the structure shown in Figure 5(a). Thus the part of the integrated circuit shown comprises an n-type silicon substrate 51 of 4 ohm-cm. resistivity and 27-5 microns t~;ickness having thereon a relatively thick silicon oxide layer part 52 of 1.0 micron thickness and a relatively thin silicon oxide layer part 53 of 1200 A thickness. The continuous line of dots 54 in-dicates the area o~er which the thin oxide layer 53 was locally removed by etching following a masking stage which involved a non-critical mask alignment.
A discrete portion 55 of a deposited layer of high resistivity polycrystalline silicon is present and the boundary of said portion is indicated by a chain line in Figure 7. The inclined hatching in Figure 7 indicates the regions where boron has been diffused.
The closely spaced inclined hatching lines within the broken line indicating the boundary of the thick oxide , layer 52 indicate ~+-diffused surface regions formed ., by diffusion in the silicon body 51 at areas where the thin oxide layer 53 has been removed. These include the source regions 57 and 58 of the transistors T3 ` and T4 respectively and the common drain region 59 .: , of these transistors. The gate electrodes of these transistor;s are formed by laterally diffused low-resistivity strip portions 61 and 62 respectively at opposite edges of the high resistivity polycrystal-line silicon layer portion 55.
.
' , , PHB 32437 ' 29.4.75 , . . . . . .
~, The upper surface of the integrated device ls covered with a deposited layer 63 of silicon oxide and within this layer apertu~es 64, 65 and 66 are pre-sent via which are respectively contacted the common drain region 59 of tlle transistors T3 and T4, the source region 57 of the transistor T3 and the source ' . ' region 58 of the transistor T4. It will be appreciat-' ed that the part of the integrated circuit shown in - plan view in Figure 7 constitutes a tes,t pattern and .~ . .
"~ 10 therefore contact apertures 64, 65 and 66 are provided.
' In a full integrated oircuit the difference resides in , i : -,~ ' that no such separate apertures are present because the ,j: . .
3~ diffused regions 57 and 58 concerned form part of ,,~ other circuit elements, viz the drain regions of~the , 15 cross-coupled pair of transistors T1 and T2 in the '~ memory cell shown in Figure 6, and the diffused re-' - gion 59 will form an inte~connection to other memory ,,J: ,: , '`"''~ '~ cells.
~, In the manufacture of the integrated device "~,; 20 shown in Figures 7 to 10, subsequent to the deposition of the polycrystalline silicon layer on the whole upper surface of the body a masking layer of silicon oxide is applied to the whole surface of the poly-crystall~ine-silicon layer. Portions of this masking '- 25 , layer ære then selectively removed together with underlying portions of the polycrystalline silicon - layer so that there remain a plurality of discrete ' _ 31 .
.
,, , , . PHB 32437 29.4.75 - . :
polycrystalline silioon portions each having its sur-face covered by-the~masking layer material of silicon oxide. This corresponds to the normal "silicon gate'~
processing and in such a pr~cess the said masking layer of silicon oxide is removed by etching in the next stage of the processing together with the portions of the thin oxide layer 53 exposed upon the selective removal of the polycrystalline silicon. The manufacs ture of the integrated device shown in Figures 7 to 10 differs from the normal "silicon gate" processing t at this stage in that prior to the said etching an additional masking of the silicon oxide layer is `i carried out using photoresist which is selectively :
exposed and developed so that over a rectangular area 68 indicated ~y the continuous line of crosses an ad-ditional masking layer of photoresist is provided.
.: . .
` Thereafter the said etching of the exposed silicon ~ ,.. .
oxide masking layer on the polycrystalline sllicon :, :
layer together with the etching of the exposed por-tions of thin ox1de layer 53 is carried out. At this stage the part of the polycrystalline layer portion 55 lylng within the rectangle 6~ thus has layers of silicon oxide and photoresist thereon. The residual portion of the photore-sist layer is now removed to leave a silicon oxide layer portion 71 on that part of the polycrystalline silicon layer portion 55 situated within the area-of the rectangle denoted .
: ` ~
- , . - PHB.32437 ~ 29.4.75.
by a line of'crosses.
The next stage in t~e processing corresponds with the normal "silicon gate" processlng in that a .' boron diffusion step is car~ied out. The difference ,,I, 5 arises, however, that for the transistors T3 and T4 ', the boron diffusion into the polycrystalline siliconto render the gate electrode portions more hlghly ~ conductive is a lateral diffusion under the silicon 'l ' ' , -oxide masking portion 71 and via the edge portions of , 10 ,the layer part 55. This results in narrow strip ' ' ' portions 61 and 62 on opposite sides of the high ' resistivity polycrystalline silicon portion 55, said ... . .
. strip portions being of 1 micron width and 30 microns ;'I , length and shown in Figures 7, 8 and 9 in crossed hatchi'hg lines. The boron.diffusion is also effect-ed into exposed portions of the polycrystalline si-- licon layer portion at the'other.two opposite ends "~, . . .
'. Or the,polycrystalline silicon layer portion 55 l . situated beyond the silicon oxide masking 71 within - ~ . 20 ' the area of the rectangle 68. The boron is also dif-. .
fused into exposed'portions of the silicon body sur-:: , . . .
~: fiace to form the source'and drain regions of the , transistors T3 and T4. Also boron diffusion is effect-' ed into the'exposed portion 69 of the polycrystalline ' 25 ' . layer~which is in direct contact with the surface of the silicon body portion within the rectangular area 54 where the thin oxide was Locally removed before - ~ ' .
29.4.75 .
the deposition of the pulycrystalline silicon layer.
This so called 'CS' (for contact silicon) contact yields the desired connection between the gate elec-trodes 61, 62 and the common drain region 59.
In this manner the laterally diffused strips 61 and 62 form gate electrodes of the transistors T3 and T4 and due to their narrow width of 1 micron and the self-regi~tration of the source a~d drain regions ~. e the channels of these transistors have an w- ratio of ; 10 approximately 30. This yields load transistors having a high series resistance of the order of 1.0 x 10 ohms with a voltage of 8 volts on the gates and com-mon drain relative to the sources.
, In this embodiment the gate electrodes formed by the laterally diffused strips 61 and 62 are joined by the remaining undiffused centre portion of the high ` resistivity polycrystalline layer portion 55. In some instances this remaining connection between the gate electrodes may be undesirable because of the diffi-culty in obtaining reproducibly a sufficiently high ; res~stlvity of the polycrystalline silicon layer in-termediate the strips and therefore a consequent .
lack of control of the effective width of the gate - electrode strips 61 and 62. Therefore in such instances :: . .
the processi~g may be suitably modified to enable the removal of the undiffused centre portion. One such adaptation of the pFeviously described process will ," , ' ' ' '' ' . .
- 34 ~
.
P~B 32ll37 . 29.~.75 now be given. In this adaptation the deviation starts with the definition of the high resistivity polycrystal-.~. .
line silicon layer into a plurality of discrete portions.
Thus, subsequent to the deposition of the high resis-tivity polycrystalline silicon layer a silicon nitride layer Of t 1 micron thickness is deposited on the . entire upper surface of the polycrystalline silicon , layer follo~ed by the deposition of a silicon oxide masking layer of 0.2 micron thickness. By a photo~
masking and etching step the upper silicon oxide .:; , , masking layer is removed according to the same mask_ ,, ing pattern as used for the definition of the poly-crystalline silicon layer into a plurality of discrete portions in the unmodified processing. The portions of "', 15 the silicon nitride layer thus exposed are then re-:!, ' moved. Thereafter all the residual portions of the : . . .
upper silicon oxide masking layer present on the re-maining silicon nitride layer portions are removed.
:,: ::~
This is followed by the removal by etching of the Z0 portions Or the polycrystalline silicon layer ex-posed where the silicon nitride layer has been re-- moved. Thus at this stage of *he processing at which the polycrystalline silicon layer has been defined as a plurali-ty of discrete portions the device is as in the normal processing with the exception that each discrete portion of the polycrystalline layer - has a silicoln nitride layer thereon instead of a ' - 3~ -.
,. .. .
.
.
r~`. :
~ .
29.4.75 .
~ 104~749 .~
- silicon oxide layer thereon. These silicon ni*ride layer portions are later selectively removed by a conventional .
plasma etching method. However prior to this plasma etching a further photomasking process is carried out, '~'' 5 using a non-critical mask alignment stage, to leave a ~ .. ! .
, , layer of photoresist on that portion of the upper sur-'' faces of the various layers within the rectangular ,' area 68 defined by the line of crosses in Figure 7.
', The plasma étching is then oarried out to remove the 'I 10 remaining exposed silicon nitride layer parts. ~th , . .
the additional photoresist layer still in place the thin oxide layer 53 is now etched' away in those areas ,.; .
'~ , where it has been exposed on account of the previous ', ' removal of the overlying polycrystalline silicon ' layer. Thu,s where bhe thin oxide layer 53 is present ~,~ withih the rectangular area 68 it is protected by the photoresist layer and therefore remains present during said etching. Following this the photoresist is removed and the boron diffusion step as described .,. ~ . . . .
, 20 in the previous embodiment is carried out to form the ~'~ ' low resistivity gaté electrode strips 61, 62, the source and d,rain electrode regions of the transis-' tors and to render more hi~hly conductive the exposed '~ ;, , upper, surface portlons of the polycrystalline silicon layer. This differs from the diffu.sion as described in the previous embodiment only in that the masking on the polycrystalline silicon portion 55 within the , , " 3~ , 29.4.75 ~ 1040749 area 68 is of silicon nitride instead of silicon oxide.
Subsequent to the boron diffusion the residual portion of the silicon nitride layer on the polyorystal-line silicon portion 55 is removed and thereafter a 5 selective etching treatment is carried out to remove the undiffused centre portion of the polycrystalline silieon portion 55 lying between the low-resistivity diffused strips 61 and 62.
The subsequent processing both for the first deseribed embodiment of the method for forming the in-. . tegrated cireuit of which part is shown in Figures 7 to 9 and for the modified, seeond deseribed embodiment of the method involves the deposition of a silicon oxide glass passivation layer 63, the opening of eontact apertures, the deposition of an interconnec-tion metal layer, the definition of said layer, -. mounting and encapsulation in accordance with con-ventionally employed processing.
; Referring now to Figures 11 to 13 a further embodiment of the method in accordance with the inven-tion will be described, In this embodiment the semi-conductor device is an integrated circuit comprising a plurality of insulated gate field effect transis-tors having ga.te electrodes formed of doped poly-crystalline silicon, the circuit being formed by a similar process as the sai~ unmodified form described with reference to Figures 7 to 10. In the embodiment - ~} _ /~ -' _ .
;;1 104~)749 now to be described the method as was employed to form the gate electrode~strips 61 and 62 by lateral diffusion in the polycrystalline silicon iayer portion in the said unmodified process, is now employed to form a crossing connection in a simple manner with the addition of only one non-critical mask alignment stage and a diffusion step. The crossing connection is between a doped poly-.~ , .
crystalline layer portion 73 and a diffused connection region comprising ~+-regions 74 and 75 at opposite ., .
sides of the'area at wh~ch the crossing occurs and further ~-type regions 79, 80 and 81. The ~ -regions 74 and 75 are formed as diffused regions bounded by the thick oxide layer 52 and these regions may be contiguous with main electrode regions of two insulat-ed gate field-effect transistors. The polycrystalline silicon layer portion 73 is in the form of a track of 10 microns width which lies on the thicker oxide ~ layer 52 with the exception of the area of the cros-,~".~ , , sing where it lies on the thinner oxide layer 53.
~, ~ 20 Within the rectangular area 76 indicated by the ~; line of crosses the polycrystalline silicon layer portion forming part of the track 73 has been left covered with a masking layer of silicon oxide on its . ': ' surface at a stage of~the processing just prior to ~- 25 the boron diffusion. This is achieved with a non-~ ,~
critical mask alignment stage. Furthermore at the opposite edges of the track the thin oxide layer 53 ,.
'.'~ , . .
- _ ~ _ .`: ' ~
, ~ , , ' PHB 32~l37 29.4.75 ~: 1040749 remains within the rectangular area 76 at this stage of the processing. The boron diffusion is carried out as - in the previously described embodiments to laterally ~ diffuse boron below the silicon oxide masking layer ::
on the traok 73 within the area 76 and form conductive strip portions 77 and 78 each of 15 microns in length :,............................................... .
and each of 1 micron width at the opposite edges of the ; track. The boron diffusion is also effected to render ~ more highly conductive the exposed upper surface ,~ 10 portions of the track 73 situated on the thick oxide layer 52 beyond the rectangular area 76. Furthermore, as the silicon surface is exposed where the thin oxide layer 53 has been removed (with the exception of within the rectangular area 76) boron is diffused in these areas to form the ~+-regions including the regions 74 and 75 which constitute parts of the connection region.
The next step in the processing is to remove the remaining portion of the silicon oxide masking layer present on the track 73 within the rectangular area 76 and to remove the portions of the thin oxide ~;~ layer 53 on opposite sides of the track 73 also with-~ in the rectangular area 76. The undiffused portion of the polycrystalline silicon track 73 between the dif-fused strip portions 77 and 78 is then removed selec-tively using a preferential etching treatment. A fur-ther boron diff`usion step is then carried out to form ~ ' , ' , .
.~; , .`_ ~ _ .
. ..
.~f ~ HB 32l~37 ~ 29.4.75 : ., .
1040~49 diffused surface regions 79 and ~0 adjacent the opposite . sides of the track where the thin oxide layer 52 has been removed. This second diffusion is also carried out to diffuse boron through the thin oxide layer 53 -5 where exposed br the selective removal of the undiffused : polycrystalline silicon track 73 and to form a p-type : surface region 81 having on its opposite sides the ~-type regions 79 and 80. ~ue to the lateral diffusion of boron in the silicon body when forming the regions 79, 80 and 81, the outer regions 79 and 80 are each spaced from the region 81 by approximately 0.5 micron.
These rrgions 79, 80 and 81 constitute parts of a ~-type diffused connection region including and extend-ing between the p -regions 74 and 75. With an n-type substrate 51 of 4 ohm-cm. resistivity the spacing (0.5 micron) of the region~ 81 from the regions 79 and , 80 is sufficiently small that the junction depletion . , ~ .
; layers where they adjoin will meet and thus complete ; the connection even when there is no applied bias across the junctions between the substrate 51 and the regions 79, 80 and 81.
; . Thus in this manner a simple crossing is . achieved between a polycrystalline silicon track 73 and an underlying diffused connection region of which , . . . .
~ 25 the p+-regions 74 and 75 form the opposite ends, be-`~ cause a) the low resistivity laterally diffused strip ~ portions 77 and 78 complete the conductive path in the ,..
.; , . .
4 :` .
~: ~ . . .
.
. PHB 32437 - 29.4.75 ' . , .
, ~0~0749 track between doped portions of the polycrystalline silicon track 73 on the thick oxide layer 52 at op~ -, - posite sides of the crossing and b) the depletion layers associated with the junctions between the . 5 p-type regions 79, 80, 81 and the n-substrate 51 ~: complete the conductive path in the connection region between the parts 74 and 75 via the diffused ~-type : reglons 79, 80 and 81.
It will be appreciated that many modifica-t.ions may be.made within the scope of the present in-vention. For example, the semiconductor body may be of a material other than silicon, the polycrystalline . semiconductor layer may be of a semiconductor material other than silicon, and materiai~ other than silicon , oxide .and silicon nitride may be used for the masking.
The embodiment in which the method in accordance with :~ the invention is used to form a crossing connection : :
:~- in an integrated circuit may be employed in the manu-. facture of integrated circuits other than the said ~silicon gate~ circuits, for example in bipolar integrated clrcuits.
~ . . ' ; ' , ~. , , , ' .
~,/ .
_ 4~
' ' ' .
~: ~ . . .
.
. PHB 32437 - 29.4.75 ' . , .
, ~0~0749 track between doped portions of the polycrystalline silicon track 73 on the thick oxide layer 52 at op~ -, - posite sides of the crossing and b) the depletion layers associated with the junctions between the . 5 p-type regions 79, 80, 81 and the n-substrate 51 ~: complete the conductive path in the connection region between the parts 74 and 75 via the diffused ~-type : reglons 79, 80 and 81.
It will be appreciated that many modifica-t.ions may be.made within the scope of the present in-vention. For example, the semiconductor body may be of a material other than silicon, the polycrystalline . semiconductor layer may be of a semiconductor material other than silicon, and materiai~ other than silicon , oxide .and silicon nitride may be used for the masking.
The embodiment in which the method in accordance with :~ the invention is used to form a crossing connection : :
:~- in an integrated circuit may be employed in the manu-. facture of integrated circuits other than the said ~silicon gate~ circuits, for example in bipolar integrated clrcuits.
~ . . ' ; ' , ~. , , , ' .
~,/ .
_ 4~
' ' ' .
Claims (18)
1. A method of manufacturing a semiconductor device in which an insulating layer is provided on a semiconductor body or body part, a layer of relatively high resistivity polycrystalline semiconductor material is deposited on the insulating layer, a masking layer is formed on a part of the exposed surface of the polycrystalline layer, a part of the polycrystalline layer is removed such that adjacent an edge portion of the masking layer the polycrystalline layer is exposed substantially throughout its thickness, and a relatively low resistivity conductive strip region having a substantially uniform narrow line width is defined in the polycrystalline layer below the masking layer by laterally diffusing a doping element into the polycrystalline layer via the exposed surface of the layer adjacent the edge portion of the masking layer.
2. A method as claimed in Claim 1, wherein subsequent to the diffusion of the doping element the masking layer is removed and the polycrystalline layer is subjected to an etch-ing treatment to selectively remove the undiffused portion and leave a relatively low resistivity diffused strip region of substantially uniform line width.
3. A method as claimed in Claim 1, wherein after the said removal of part of the polycrystalline layer there is first diffused into the exposed surface of the polycrystalline layer a doping element characteristic of one conductivity type and thereafter there is diffused a doping element characteris-tic of the opposite conductivity type in a higher concentra-tion but to a lesser distance laterally in the layer so that a p-n junction extending substantially in the direction of thick-ness of the layer is formed between the outermost diffused region characteristic of the opposite conductivity type and the adjoining diffused region characteristic of the one conductivity type which is of substantially uniform width and situated below the masking layer.
4. A method as claimed in Claim 3, wherein subsequent to the second diffusion the masking layer is removed and the polycrystalline layer is subjected to an etching treatment to selectively remove the outermost diffused region of the opposite conductivity type and the undiffused portion of the layer and leave a relatively low resistivity diffused strip region of the one conductivity type and of substantially uniform width.
5. A method as claimed in Claim 1, wherein the device manufactured comprises at least one insulated gate field effect transistor and at least part of the relatively low resistivity strip region formed in the polycrystalline semiconductor layer constitutes at least part of the gate electrode of the transis-tor.
6. A method as claimed in Claim 5, wherein subsequent to the diffusion of the doping element the masking layer is removed and the polycrystalline layer is subjected to an etch-ing treatment to selectively remove the undiffused portion and leave a relatively low resistivity diffused strip region of substantially uniform line width and subsequent to the selective etching treatment at least parts of the source and drain regions of the transistor are formed by impurity introduction into the semiconductor body at opposite sides of the diffused strip region formed in the polycrystalline layer, said strip region masking against impurity introduction into the portion of the semiconductor body lying below said strip region.
7. A method as claimed in Claim 5, wherein the semi-conductor device is an integrated circuit comprising a plur-ality of insulated gate field effect transistors having their gate electrodes formed by doped portions of the polycrystalline semiconductor layer, the said insulated gate field effect tran-sistor in which at least part of the strip-region formed in the polycrystalline layer constitutes at least part of the gate electrode being formed as a load transistor and having the gate electrode connected to the drain region.
8. A method as claimed in Claim 7, wherein the inte-grated circuit comprises two of the said transistors formed as loads and having their gate electrodes connected to a common drain region, the gate electrodes of said two transistors comprising laterally diffused strip regions formed in the polycrystalline layer, which regions each are of substantially uniform width and are situated at opposite edges of a single part of the polycrystalline layer.
9. A method as claimed in Claim 8, wherein the diffusion to form the gate electrode strip regions of the polycrystalline layer, which is effected in the presence of a masking layer locally present on said part of the polycrystalline layer, is carried out simultaneously with the diffusion to form at least part of the source and drain regions of the transistors and to render more highly conductive other exposed portions of the polycrystalline layer.
10. A method as claimed in Claim 9, wherein the masking layer comprises a residual part of a layer provided at the surface of the polycrystalline layer and employed for the previous definition of the polycrystalline layer into a plurality of discrete parts.
11. A method as claimed in Claim 7, wherein the semi-conductor device is an integrated circuit and at least one portion of the polycrystalline semiconductor layer constitutes a conductive track which crosses and is insulated from an underlying diffused connection region in the semiconductor body, the opposite edge portions of the track at the area of the crossing being converted into low resistivity diffused strip regions by the said lateral diffusion in the presence of a mask-ing layer on the track at the area of the crossing.
12. A method as claimed in Claim 11, wherein the integrated circuit comprises a plurality of insulated gate field effect transistors having their gate electrodes formed by doped portions of the polycrystalline semiconductor layer, the said lateral diffusion being carried out simultaneously with a diffusion to form at least parts of the source and drain regions of transistors and to dope exposed upper surface portions of the polycrystalline semiconductor layer.
13. A method as claimed in Claim 11, wherein subsequent to forming the low resistivity diffused strip regions at the opposite edge portions of the track at the area of the crossing, the undiffused central portion of the track at the area of the crossing is selectively removed and a further diffusion is carried out to form at the area of the crossing a diffused sur-face region in the semiconductor body in the form of a strip situated intermediate the portions of the body above which the low resistivity diffused strip regions of the track are present, said diffused surface region forming part of the diffused connec-tion region.
14. A method as claimed in Claim 13, wherein the further diffusion step is also carried out to form at the area of the crossing diffused surface regions in the semiconductor body situated adjacent and extending inwardly below the said opposite edges of the track at which the low resistivity diffused strip regions have been formed, said diffused surface regions forming parts of the diffused connection region.
15. A method of manufacturing a semiconductor device in which an insulating layer is provided on a semiconductor body or body part, a layer of relatively high resistivity polycry-stalline semi conductor material is deposited on the insulating layer, a masking layer is formed on a part of the surface of the polycrystalline layer, a relatively low resistivity conductive strip region having a substantially uniform narrow line width is defined in the polycrystalline layer below the masking layer by effecting at least one diffusion process in which a lateral diffusion of a doping element is effected into the polycrystal-line layer below an edge portion of the masking layer, the mask-ing layer is removed and the polycrystalline layer is subjected to an etching treatment to selectively remove the said low resistivity conductive strip region or to selectively remove layer parts adjoining the low resistivity conductive strip region.
16. A method as claimed in Claim 15, wherein the masking layer is of smaller area than the polycrystalline layer on which it is present so that adjacent the edge portion of the masking layer the upper surface of the polycrystalline layer is exposed, the diffusion process comprising first diffusing a dopant element characteristic of one conductivity type into said exposed surface such that lateral diffusion of the element occurs under the masking layer and then diffusing a doping element characteristic of the opposite conductivity type into said exposed surface in a higher concentration but to a lesser distance laterally in the layer so that a p-n junction extending substantially in the direction of thickness of the layer is formed under the masking layer between the outermost diffused region of the opposite conductivity type and the adjoining diffused region of the one conductivity type of substantially uniform width and extending under the masking layer.
17. A method as claimed in Claim 16, wherein subsequent to the diffusion process the masking layer is removed and the polycrystalline layer subjected to an etching treatment to selec-tively remove only the relatively narrow diffused region of the one conductivity type and thereby form in the polycrystalline layer an aperture of relatively narrow and substantially uniform width.
18. A method as claimed in Claim 15, wherein the device manufactured comprises at least one insulated gate field effect transistor, the selective etching is effected by remove layer parts adjoining the low resistivity conductive strip region and at least part of the remaining low resistivity strip region formed in the polycrystalline semiconductor layer constitutes at least part of the gate electrode of the transistor.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB2258374A GB1477511A (en) | 1974-05-21 | 1974-05-21 | Methods of manufacturing semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1040749A true CA1040749A (en) | 1978-10-17 |
Family
ID=10181779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA227,266A Expired CA1040749A (en) | 1974-05-21 | 1975-05-15 | Method of manufacturing fine line conductors on semiconductors |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5617826B2 (en) |
| CA (1) | CA1040749A (en) |
| DE (1) | DE2522448A1 (en) |
| FR (1) | FR2272486B1 (en) |
| GB (1) | GB1477511A (en) |
| NL (1) | NL7505698A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4013489A (en) * | 1976-02-10 | 1977-03-22 | Intel Corporation | Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit |
| JPS598855Y2 (en) * | 1978-09-01 | 1984-03-19 | 大阪電気株式会社 | wire feeding device |
| JPS5546570A (en) * | 1978-09-30 | 1980-04-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Method of fabricating mos semiconductor device |
| US4298402A (en) * | 1980-02-04 | 1981-11-03 | Fairchild Camera & Instrument Corp. | Method of fabricating self-aligned lateral bipolar transistor utilizing special masking techniques |
| JPS6070401U (en) * | 1983-10-24 | 1985-05-18 | 株式会社月星製作所 | wheel spokes |
| CN111665669A (en) * | 2015-01-08 | 2020-09-15 | 群创光电股份有限公司 | Display panel |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5542501B2 (en) * | 1974-01-29 | 1980-10-31 |
-
1974
- 1974-05-21 GB GB2258374A patent/GB1477511A/en not_active Expired
-
1975
- 1975-05-15 NL NL7505698A patent/NL7505698A/en not_active Application Discontinuation
- 1975-05-15 CA CA227,266A patent/CA1040749A/en not_active Expired
- 1975-05-21 DE DE19752522448 patent/DE2522448A1/en not_active Withdrawn
- 1975-05-21 FR FR7515787A patent/FR2272486B1/fr not_active Expired
- 1975-05-21 JP JP5979875A patent/JPS5617826B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2272486A1 (en) | 1975-12-19 |
| DE2522448A1 (en) | 1975-12-04 |
| FR2272486B1 (en) | 1979-01-19 |
| JPS5617826B2 (en) | 1981-04-24 |
| NL7505698A (en) | 1975-11-25 |
| GB1477511A (en) | 1977-06-22 |
| JPS51282A (en) | 1976-01-05 |
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