DE2519432A1 - Verfahren zur herstellung dotierter vergrabener zonen in einem halbleiterkoerper - Google Patents

Verfahren zur herstellung dotierter vergrabener zonen in einem halbleiterkoerper

Info

Publication number
DE2519432A1
DE2519432A1 DE19752519432 DE2519432A DE2519432A1 DE 2519432 A1 DE2519432 A1 DE 2519432A1 DE 19752519432 DE19752519432 DE 19752519432 DE 2519432 A DE2519432 A DE 2519432A DE 2519432 A1 DE2519432 A1 DE 2519432A1
Authority
DE
Germany
Prior art keywords
semiconductor body
layer
implanted
ions
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19752519432
Other languages
German (de)
English (en)
Inventor
Kon Ho Cho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE2519432A1 publication Critical patent/DE2519432A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67—Complementary BJTs
    • H10D84/673—Vertical complementary BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/007—Autodoping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/017—Clean surfaces
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/92—Controlling diffusion profile by oxidation

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
DE19752519432 1974-05-03 1975-04-30 Verfahren zur herstellung dotierter vergrabener zonen in einem halbleiterkoerper Pending DE2519432A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US466920A US3909304A (en) 1974-05-03 1974-05-03 Method of doping a semiconductor body

Publications (1)

Publication Number Publication Date
DE2519432A1 true DE2519432A1 (de) 1975-11-13

Family

ID=23853591

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752519432 Pending DE2519432A1 (de) 1974-05-03 1975-04-30 Verfahren zur herstellung dotierter vergrabener zonen in einem halbleiterkoerper

Country Status (6)

Country Link
US (1) US3909304A (OSRAM)
JP (1) JPS5118473A (OSRAM)
CA (1) CA1023059A (OSRAM)
DE (1) DE2519432A1 (OSRAM)
FR (1) FR2269790B1 (OSRAM)
GB (1) GB1468131A (OSRAM)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179311A (en) * 1977-01-17 1979-12-18 Mostek Corporation Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides
US4584763A (en) * 1983-12-15 1986-04-29 International Business Machines Corporation One mask technique for substrate contacting in integrated circuits involving deep dielectric isolation
JPH0397224A (ja) * 1989-09-11 1991-04-23 Toshiba Corp 半導体装置の製造方法
US5358881A (en) * 1993-05-19 1994-10-25 Hewlett-Packard Company Silicon topography control method
US6780718B2 (en) 1993-11-30 2004-08-24 Stmicroelectronics, Inc. Transistor structure and method for making same
US6171966B1 (en) * 1996-08-15 2001-01-09 Applied Materials, Inc. Delineation pattern for epitaxial depositions
US6452338B1 (en) 1999-12-13 2002-09-17 Semequip, Inc. Electron beam ion source with integral low-temperature vaporizer
US8572800B2 (en) 2009-11-12 2013-11-05 Haan Corporation Base assembly for sweeper
KR20130139738A (ko) * 2011-01-17 2013-12-23 스미토모덴키고교가부시키가이샤 탄화규소 반도체 장치의 제조방법
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US10224233B2 (en) 2014-11-18 2019-03-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation
CN114496732B (zh) 2015-06-01 2023-03-03 环球晶圆股份有限公司 制造绝缘体上硅锗的方法
JP6749394B2 (ja) 2015-11-20 2020-09-02 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 滑らかな半導体表面の製造方法
US10269617B2 (en) * 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
CN118943075A (zh) 2018-06-08 2024-11-12 环球晶圆股份有限公司 将硅薄层移转的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL135876C (OSRAM) * 1963-06-11
US3655457A (en) * 1968-08-06 1972-04-11 Ibm Method of making or modifying a pn-junction by ion implantation
US3764396A (en) * 1969-09-18 1973-10-09 Kogyo Gijutsuin Transistors and production thereof
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
AU464038B2 (en) * 1970-12-09 1975-08-14 Philips Nv Improvements in and relating to semiconductor devices
US3793088A (en) * 1972-11-15 1974-02-19 Bell Telephone Labor Inc Compatible pnp and npn devices in an integrated circuit

Also Published As

Publication number Publication date
GB1468131A (en) 1977-03-23
JPS5118473A (en) 1976-02-14
CA1023059A (en) 1977-12-20
FR2269790B1 (OSRAM) 1978-06-30
JPS5325788B2 (OSRAM) 1978-07-28
US3909304A (en) 1975-09-30
FR2269790A1 (OSRAM) 1975-11-28

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