DE2320420A1 - Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen - Google Patents

Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen

Info

Publication number
DE2320420A1
DE2320420A1 DE2320420A DE2320420A DE2320420A1 DE 2320420 A1 DE2320420 A1 DE 2320420A1 DE 2320420 A DE2320420 A DE 2320420A DE 2320420 A DE2320420 A DE 2320420A DE 2320420 A1 DE2320420 A1 DE 2320420A1
Authority
DE
Germany
Prior art keywords
layer
connection pattern
areas
semiconductor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2320420A
Other languages
German (de)
English (en)
Inventor
Ronald Roy Troutman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2320420A1 publication Critical patent/DE2320420A1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0198Integrating together multiple components covered by H10D44/00, e.g. integrating charge coupled devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/15Charge-coupled device [CCD] image sensors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/934Sheet resistance, i.e. dopant parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE2320420A 1972-06-30 1973-04-21 Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen Pending DE2320420A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00267860A US3810795A (en) 1972-06-30 1972-06-30 Method for making self-aligning structure for charge-coupled and bucket brigade devices

Publications (1)

Publication Number Publication Date
DE2320420A1 true DE2320420A1 (de) 1974-01-17

Family

ID=23020423

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2320420A Pending DE2320420A1 (de) 1972-06-30 1973-04-21 Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen

Country Status (5)

Country Link
US (1) US3810795A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5637707B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2320420A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2191269B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1425864A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3967306A (en) * 1973-08-01 1976-06-29 Trw Inc. Asymmetrical well charge coupled device
US3927468A (en) * 1973-12-28 1975-12-23 Fairchild Camera Instr Co Self aligned CCD element fabrication method therefor
US3911560A (en) * 1974-02-25 1975-10-14 Fairchild Camera Instr Co Method for manufacturing a semiconductor device having self-aligned implanted barriers with narrow gaps between electrodes
US4053349A (en) * 1976-02-02 1977-10-11 Intel Corporation Method for forming a narrow gap
IT1089299B (it) * 1977-01-26 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
JPS5910581B2 (ja) * 1977-12-01 1984-03-09 富士通株式会社 半導体装置の製造方法
US4933297A (en) * 1989-10-12 1990-06-12 At&T Bell Laboratories Method for etching windows having different depths
US7846760B2 (en) * 2006-05-31 2010-12-07 Kenet, Inc. Doped plug for CCD gaps

Also Published As

Publication number Publication date
JPS4959581A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-06-10
FR2191269A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-02-01
GB1425864A (en) 1976-02-18
JPS5637707B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1981-09-02
US3810795A (en) 1974-05-14
FR2191269B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1977-09-09

Similar Documents

Publication Publication Date Title
DE2745857C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE4116690C2 (de) Elementisolationsaufbau einer Halbleitereinrichtung und Verfahren zur Herstellung derselben
DE2502235C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE3019850C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE3881799T2 (de) Verfahren zur Herstellung von CMOS-Bauelementen.
EP0071665B1 (de) Verfahren zum Herstellen einer monolithisch integrierten Festkörperschaltung mit mindestens einem bipolaren Planartransistor
DE2335799A1 (de) Sperrschicht-feldeffekttransistoren in dielektrisch isolierten mesas
DE2749607C3 (de) Halbleiteranordnung und Verfahren zu deren Herstellung
DE2314260A1 (de) Ladungsgekoppelte halbleiteranordnung und verfahren zu ihrer herstellung
DE3116268C2 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE2605830A1 (de) Verfahren zur herstellung von halbleiterbauelementen
DE3030385A1 (de) Mos-halbleitervorrichtung und verfahren zur herstellung derselben
DE2922015A1 (de) Verfahren zur herstellung einer vlsi-schaltung
DE2926334C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE4130555A1 (de) Halbleitervorrichtung mit hoher durchbruchsspannung und geringem widerstand, sowie herstellungsverfahren
DE2729973A1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE1803024A1 (de) Integriertes Halbleiterbauelement und Verfahren zu seiner Herstellung
DE2133976B2 (de) Monolithisch integrierte Halbleiteranordnung
DE2320420A1 (de) Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen
DE2541651C2 (de) Verfahren zur Herstellung einer Ladungsübertragungsanordnung
DE2932928A1 (de) Verfahren zur herstellung von vlsi-schaltungen
DE2141695B2 (de) Verfahren zum herstellen eines monolithischen halbleiterbauelementes
WO2003015163A2 (de) Verfahren zum parallelen herstellen eines mos-transistors und eines bipolartransistors
DE2525529B2 (de) Halbleiteranordnung mit komplementaeren transistorstrukturen und verfahren zu ihrer herstellung
DE2535272A1 (de) Festkoerperbauelement-herstellungsverfahren

Legal Events

Date Code Title Description
OHJ Non-payment of the annual fee