DE2238687A1 - Binaere addieranordnung - Google Patents

Binaere addieranordnung

Info

Publication number
DE2238687A1
DE2238687A1 DE19722238687 DE2238687A DE2238687A1 DE 2238687 A1 DE2238687 A1 DE 2238687A1 DE 19722238687 DE19722238687 DE 19722238687 DE 2238687 A DE2238687 A DE 2238687A DE 2238687 A1 DE2238687 A1 DE 2238687A1
Authority
DE
Germany
Prior art keywords
memory
pair
arrangement according
output
associative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19722238687
Other languages
German (de)
English (en)
Inventor
Peter Lycett Gardner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2238687A1 publication Critical patent/DE2238687A1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5057—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using table look-up; using programmable logic arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4804—Associative memory or processor

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE19722238687 1971-09-10 1972-08-05 Binaere addieranordnung Pending DE2238687A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4223871 1971-09-10

Publications (1)

Publication Number Publication Date
DE2238687A1 true DE2238687A1 (de) 1973-03-22

Family

ID=10423492

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19722238687 Pending DE2238687A1 (de) 1971-09-10 1972-08-05 Binaere addieranordnung

Country Status (4)

Country Link
JP (1) JPS5526749B2 (enExample)
DE (1) DE2238687A1 (enExample)
FR (1) FR2151977A5 (enExample)
GB (1) GB1322657A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2952689A1 (de) * 1979-01-03 1980-07-17 Burroughs Corp Programmierbarer lesespeicher-addierer

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4157590A (en) * 1978-01-03 1979-06-05 International Business Machines Corporation Programmable logic array adder
GB2011669B (en) * 1978-01-03 1982-01-13 Ibm Programmable logic array adders
JPS5960617A (ja) * 1982-09-30 1984-04-06 Fujitsu Denso Ltd 共振形定電流回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2952689A1 (de) * 1979-01-03 1980-07-17 Burroughs Corp Programmierbarer lesespeicher-addierer

Also Published As

Publication number Publication date
JPS5526749B2 (enExample) 1980-07-15
GB1322657A (en) 1973-07-11
JPS4838038A (enExample) 1973-06-05
FR2151977A5 (enExample) 1973-04-20

Similar Documents

Publication Publication Date Title
DE2930441C2 (de) Anzeigeeinrichtung zur wahlweisen dynamischen oder statischen Anzeige
DE2814078A1 (de) Addierschaltung mit zeitweiliger zwischenspeicherung des uebertrags
DE2706807C2 (de) Einrichtung und Verfahren zum Verarbeiten von Information in Form digitaler Signale
DE2848096C3 (de) Digitale Addieranordnung
DE1079358B (de) Dezimal-Addiervorrichtung
DE3340362C2 (enExample)
DE2238687A1 (de) Binaere addieranordnung
DE1774675A1 (de) Elektronisches Rechengeraet
DE1499227C3 (de) Schaltungsanordnung für arithmetische und logische Grundoperationen
DE1774606B1 (de) Speicheranordnung zur durchfuehrung logischer und arithmetischer grundoperationen
DE1241159B (de) UEbertragschaltung fuer ein Schnelladdierwerk
DE1774771A1 (de) Anordnung,um wechselweise eine Addition oder eine aus einer Anzahl logischer Funktionen zwischen den Inhalten einer Stelle zweier Binaerworte durchzufuehren
DE1948387A1 (de) Arithmetische und logische Einheit
DE2022256A1 (de) Permanentspeicher
DE2511673C2 (de) Schaltung zur Übertragung eines Feldes zwischen zwei Registern unter Mitwirkung einer Schiebeschaltung
DE1085357B (de) Stellenwertverschiebung in Informationswandlern
DE2316904A1 (de) Informationseingabevorrichtung
DE2500201A1 (de) Zeichenoperator fuer binaer codierte dezimalziffern
DE2057124A1 (de) Assoziativspeicher
DE1808159B2 (de) Einrichtung zur umsetzung von dualzahlen in binaer codierte dezimalzahlen in paralleler darstellung
DE2948340A1 (de) Informationsuebertragungssystem
DE1157009B (de) Rechenwerk einer digitalen Rechenmaschine
DE1099236B (de) Elektrisches Rechenwerk zum Potenzieren einer ªÃ-stelligen binaeren Zahl
DE1774606C (de) Speicheranordnung zur Durchführung logischer und arithmetischer Grundoperationen
DE1549483A1 (de) Schaltungsanordnung zur Durchfuehrung logischer und arithmetischer Grundoperationen

Legal Events

Date Code Title Description
OHJ Non-payment of the annual fee