DE2124772C3 - Verfahren zur Herstellung von Halbleiterbauelementen - Google Patents

Verfahren zur Herstellung von Halbleiterbauelementen

Info

Publication number
DE2124772C3
DE2124772C3 DE2124772A DE2124772A DE2124772C3 DE 2124772 C3 DE2124772 C3 DE 2124772C3 DE 2124772 A DE2124772 A DE 2124772A DE 2124772 A DE2124772 A DE 2124772A DE 2124772 C3 DE2124772 C3 DE 2124772C3
Authority
DE
Germany
Prior art keywords
network
semiconductor components
semiconductor
components
mass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2124772A
Other languages
German (de)
English (en)
Other versions
DE2124772A1 (de
DE2124772B2 (de
Inventor
Dennis George Handsworth Wood Birmingham Goodman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZF International UK Ltd
Original Assignee
Joseph Lucas Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Joseph Lucas Industries Ltd filed Critical Joseph Lucas Industries Ltd
Publication of DE2124772A1 publication Critical patent/DE2124772A1/de
Publication of DE2124772B2 publication Critical patent/DE2124772B2/de
Application granted granted Critical
Publication of DE2124772C3 publication Critical patent/DE2124772C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Weting (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
DE2124772A 1970-05-21 1971-05-19 Verfahren zur Herstellung von Halbleiterbauelementen Expired DE2124772C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2455070 1970-05-21

Publications (3)

Publication Number Publication Date
DE2124772A1 DE2124772A1 (de) 1971-12-02
DE2124772B2 DE2124772B2 (de) 1975-08-28
DE2124772C3 true DE2124772C3 (de) 1981-10-22

Family

ID=10213386

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2124772A Expired DE2124772C3 (de) 1970-05-21 1971-05-19 Verfahren zur Herstellung von Halbleiterbauelementen

Country Status (7)

Country Link
US (1) US3708870A (https=)
JP (1) JPS5131072B1 (https=)
DE (1) DE2124772C3 (https=)
FR (1) FR2090182B1 (https=)
GB (1) GB1335201A (https=)
NL (1) NL7106948A (https=)
ZA (1) ZA712698B (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3978578A (en) * 1974-08-29 1976-09-07 Fairchild Camera And Instrument Corporation Method for packaging semiconductor devices
US5026667A (en) * 1987-12-29 1991-06-25 Analog Devices, Incorporated Producing integrated circuit chips with reduced stress effects
US5306370A (en) * 1992-11-02 1994-04-26 Xerox Corporation Method of reducing chipping and contamination of reservoirs and channels in thermal ink printheads during dicing by vacuum impregnation with protective filler material
FR2877142B1 (fr) * 2004-10-21 2007-05-11 Commissariat Energie Atomique Procede de transfert d'au moins un objet de taille micrometrique ou millimetrique au moyen d'une poignee en polymere.

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3313013A (en) * 1960-08-15 1967-04-11 Fairchild Camera Instr Co Method of making solid-state circuitry
FR1400084A (fr) * 1963-07-03 1965-05-21 Ibm Procédé de revêtement de semiconducteurs
DE1514453A1 (de) * 1965-04-26 1969-08-14 Siemens Ag Verfahren zum Herstellen von Halbleiterschaltungen
US3313661A (en) * 1965-05-14 1967-04-11 Dickson Electronics Corp Treating of surfaces of semiconductor elements
US3355636A (en) * 1965-06-29 1967-11-28 Rca Corp High power, high frequency transistor
GB1285708A (en) * 1968-10-28 1972-08-16 Lucas Industries Ltd Semi-conductor devices
US3633269A (en) * 1969-06-24 1972-01-11 Telefunken Patent Method of making contact to semiconductor devices

Also Published As

Publication number Publication date
NL7106948A (https=) 1971-11-23
FR2090182A1 (https=) 1972-01-14
US3708870A (en) 1973-01-09
JPS5131072B1 (https=) 1976-09-04
GB1335201A (en) 1973-10-24
ZA712698B (en) 1972-01-26
FR2090182B1 (https=) 1974-04-05
DE2124772A1 (de) 1971-12-02
DE2124772B2 (de) 1975-08-28

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee