DE2066108C2 - Verfahren zum Herstellen elektrischer Leitungsverbindungen auf einem Halbleitersubstrat mit einem p-n-Übergang - Google Patents

Verfahren zum Herstellen elektrischer Leitungsverbindungen auf einem Halbleitersubstrat mit einem p-n-Übergang

Info

Publication number
DE2066108C2
DE2066108C2 DE2066108A DE2066108A DE2066108C2 DE 2066108 C2 DE2066108 C2 DE 2066108C2 DE 2066108 A DE2066108 A DE 2066108A DE 2066108 A DE2066108 A DE 2066108A DE 2066108 C2 DE2066108 C2 DE 2066108C2
Authority
DE
Germany
Prior art keywords
substrate
layer
junction
anodizing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2066108A
Other languages
German (de)
English (en)
Inventor
Hiroshi Shiba
Hideo Shiba Tokio/Tokyo Tsunemitsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP8535869A external-priority patent/JPS5123854B1/ja
Priority claimed from JP8707269A external-priority patent/JPS5754942B1/ja
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Application granted granted Critical
Publication of DE2066108C2 publication Critical patent/DE2066108C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/022—Anodisation on selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/04—Anodisation of aluminium or alloys based thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE2066108A 1969-10-25 1970-10-26 Verfahren zum Herstellen elektrischer Leitungsverbindungen auf einem Halbleitersubstrat mit einem p-n-Übergang Expired DE2066108C2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8535869A JPS5123854B1 (enExample) 1969-10-25 1969-10-25
JP8707269A JPS5754942B1 (enExample) 1969-10-30 1969-10-30

Publications (1)

Publication Number Publication Date
DE2066108C2 true DE2066108C2 (de) 1985-04-04

Family

ID=26426376

Family Applications (2)

Application Number Title Priority Date Filing Date
DE2066108A Expired DE2066108C2 (de) 1969-10-25 1970-10-26 Verfahren zum Herstellen elektrischer Leitungsverbindungen auf einem Halbleitersubstrat mit einem p-n-Übergang
DE2052424A Expired DE2052424C3 (de) 1969-10-25 1970-10-26 Verfahren zum Herstellen elektrischer Leitungsverbindungen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE2052424A Expired DE2052424C3 (de) 1969-10-25 1970-10-26 Verfahren zum Herstellen elektrischer Leitungsverbindungen

Country Status (7)

Country Link
US (1) US3741880A (enExample)
DE (2) DE2066108C2 (enExample)
FR (1) FR2066471A5 (enExample)
GB (2) GB1342487A (enExample)
HK (2) HK28976A (enExample)
MY (2) MY7600038A (enExample)
NL (1) NL172388B (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3939047A (en) * 1971-11-15 1976-02-17 Nippon Electric Co., Ltd. Method for fabricating electrode structure for a semiconductor device having a shallow junction
US3827949A (en) * 1972-03-29 1974-08-06 Ibm Anodic oxide passivated planar aluminum metallurgy system and method of producing
JPS557019B2 (enExample) * 1972-05-10 1980-02-21
JPS4995591A (enExample) * 1973-01-12 1974-09-10
JPS4995592A (enExample) * 1973-01-12 1974-09-10
US3864217A (en) * 1974-01-21 1975-02-04 Nippon Electric Co Method of fabricating a semiconductor device
US3918148A (en) * 1974-04-15 1975-11-11 Ibm Integrated circuit chip carrier and method for forming the same
US3882000A (en) * 1974-05-09 1975-05-06 Bell Telephone Labor Inc Formation of composite oxides on III-V semiconductors
FR2285716A1 (fr) * 1974-09-18 1976-04-16 Radiotechnique Compelec Procede pour la fabrication d'un dispositif semi-conducteur comportant une configuration de conducteurs et dispositif fabrique par ce procede
US3971710A (en) * 1974-11-29 1976-07-27 Ibm Anodized articles and process of preparing same
US4056681A (en) * 1975-08-04 1977-11-01 International Telephone And Telegraph Corporation Self-aligning package for integrated circuits
US4045302A (en) * 1976-07-08 1977-08-30 Burroughs Corporation Multilevel metallization process
US4158613A (en) * 1978-12-04 1979-06-19 Burroughs Corporation Method of forming a metal interconnect structure for integrated circuits
US4161430A (en) * 1978-12-04 1979-07-17 Burroughs Corporation Method of forming integrated circuit metal interconnect structure employing molybdenum on aluminum
DE2902665A1 (de) * 1979-01-24 1980-08-07 Siemens Ag Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie
FR2510307A1 (fr) * 1981-07-24 1983-01-28 Hitachi Ltd Dispositif a semi-conducteurs et procede de fabrication d'un tel dispositif
US4517616A (en) * 1982-04-12 1985-05-14 Memorex Corporation Thin film magnetic recording transducer having embedded pole piece design
US4391849A (en) * 1982-04-12 1983-07-05 Memorex Corporation Metal oxide patterns with planar surface
JPS60132353A (ja) * 1983-12-20 1985-07-15 Mitsubishi Electric Corp 半導体装置の製造方法
US5141603A (en) * 1988-03-28 1992-08-25 The United States Of America As Represented By The Secretary Of The Air Force Capacitor method for improved oxide dielectric
US4936957A (en) * 1988-03-28 1990-06-26 The United States Of America As Represented By The Secretary Of The Air Force Thin film oxide dielectric structure and method
US5098860A (en) * 1990-05-07 1992-03-24 The Boeing Company Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers
LT4425B (lt) 1995-04-28 1998-12-28 Monika Paszkowska Termodinaminis aspiracinis vožtuvas
JP4882229B2 (ja) * 2004-09-08 2012-02-22 株式会社デンソー 半導体装置およびその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3337426A (en) * 1964-06-04 1967-08-22 Gen Dynamics Corp Process for fabricating electrical circuits
DE1292759B (de) * 1963-08-28 1969-04-17 Itt Ind Gmbh Deutsche Verfahren zum Herstellen einer Zuleitung zu einer diffundierten Halbleiterzone

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1292759B (de) * 1963-08-28 1969-04-17 Itt Ind Gmbh Deutsche Verfahren zum Herstellen einer Zuleitung zu einer diffundierten Halbleiterzone
US3337426A (en) * 1964-06-04 1967-08-22 Gen Dynamics Corp Process for fabricating electrical circuits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
In Betracht gezogene ältere Anmeldung: DE-OS 19 30 669 *

Also Published As

Publication number Publication date
FR2066471A5 (enExample) 1971-08-06
DE2052424B2 (de) 1979-03-22
HK28976A (en) 1976-05-28
DE2052424C3 (de) 1979-11-15
HK28876A (en) 1976-05-28
US3741880A (en) 1973-06-26
NL7015610A (enExample) 1971-04-27
MY7600037A (en) 1976-12-31
GB1342487A (en) 1974-01-03
MY7600038A (en) 1976-12-31
NL172388B (nl) 1983-03-16
DE2052424A1 (de) 1971-09-30
GB1342486A (en) 1974-01-03

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