DE19622650A1 - Gehäuse für digitalen Hochleistungs-IC, welcher ein BGA(Kugelgitterarray)-Ein/Ausgabe-Format verwendet sowie keramisches Einschicht-Substrat mit Bimetall gefüllter Durchgangstechnologie - Google Patents

Gehäuse für digitalen Hochleistungs-IC, welcher ein BGA(Kugelgitterarray)-Ein/Ausgabe-Format verwendet sowie keramisches Einschicht-Substrat mit Bimetall gefüllter Durchgangstechnologie

Info

Publication number
DE19622650A1
DE19622650A1 DE19622650A DE19622650A DE19622650A1 DE 19622650 A1 DE19622650 A1 DE 19622650A1 DE 19622650 A DE19622650 A DE 19622650A DE 19622650 A DE19622650 A DE 19622650A DE 19622650 A1 DE19622650 A1 DE 19622650A1
Authority
DE
Germany
Prior art keywords
housing
integrated circuit
digital integrated
circuit according
approximately
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19622650A
Other languages
German (de)
English (en)
Inventor
Norman L Greenman
M P Ramachandra Panicker
Jorge M Hernandez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Circuit Components Inc
Original Assignee
Circuit Components Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Circuit Components Inc filed Critical Circuit Components Inc
Publication of DE19622650A1 publication Critical patent/DE19622650A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/153—Containers comprising an insulating or insulated base having interconnections in passages through the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
DE19622650A 1995-06-06 1996-06-05 Gehäuse für digitalen Hochleistungs-IC, welcher ein BGA(Kugelgitterarray)-Ein/Ausgabe-Format verwendet sowie keramisches Einschicht-Substrat mit Bimetall gefüllter Durchgangstechnologie Withdrawn DE19622650A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US47109595A 1995-06-06 1995-06-06

Publications (1)

Publication Number Publication Date
DE19622650A1 true DE19622650A1 (de) 1996-12-12

Family

ID=23870234

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19622650A Withdrawn DE19622650A1 (de) 1995-06-06 1996-06-05 Gehäuse für digitalen Hochleistungs-IC, welcher ein BGA(Kugelgitterarray)-Ein/Ausgabe-Format verwendet sowie keramisches Einschicht-Substrat mit Bimetall gefüllter Durchgangstechnologie

Country Status (6)

Country Link
JP (1) JPH09213829A (oth)
KR (1) KR970003879A (oth)
DE (1) DE19622650A1 (oth)
GB (1) GB2301937A (oth)
MX (1) MXPA96002171A (oth)
TW (1) TW299487B (oth)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054338A (en) * 1996-05-17 2000-04-25 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
DE10010461A1 (de) * 2000-03-03 2001-09-13 Infineon Technologies Ag Vorrichtung zum Verpacken elektronischer Bauteile mittels Spritzgußtechnik
EP0997934A3 (en) * 1998-08-26 2002-09-04 Elliott Industries Limited An electronic component package assembly and method of manufacturing the same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11219984A (ja) * 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6198166B1 (en) * 1999-07-01 2001-03-06 Intersil Corporation Power semiconductor mounting package containing ball grid array
GB2377080B (en) * 2001-09-11 2003-05-07 Sendo Int Ltd Integrated circuit package and printed circuit board arrangement
JP6397806B2 (ja) 2015-09-11 2018-09-26 東芝メモリ株式会社 半導体装置の製造方法および半導体装置
WO2026078946A1 (ja) * 2024-10-09 2026-04-16 株式会社村田製作所 モジュール

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
TW272311B (oth) * 1994-01-12 1996-03-11 At & T Corp

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054338A (en) * 1996-05-17 2000-04-25 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
DE19820319B4 (de) * 1997-07-08 2005-12-01 National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara Halbleiterbaustein
EP0997934A3 (en) * 1998-08-26 2002-09-04 Elliott Industries Limited An electronic component package assembly and method of manufacturing the same
DE10010461A1 (de) * 2000-03-03 2001-09-13 Infineon Technologies Ag Vorrichtung zum Verpacken elektronischer Bauteile mittels Spritzgußtechnik

Also Published As

Publication number Publication date
JPH09213829A (ja) 1997-08-15
TW299487B (oth) 1997-03-01
GB9611726D0 (en) 1996-08-07
KR970003879A (ko) 1997-01-29
GB2301937A (en) 1996-12-18
MXPA96002171A (es) 2002-04-19

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8139 Disposal/non-payment of the annual fee