DE19549155C2 - Verfahren zum Isolieren von Halbleitereinrichtungen in einem Siliziumsubstrat - Google Patents
Verfahren zum Isolieren von Halbleitereinrichtungen in einem SiliziumsubstratInfo
- Publication number
- DE19549155C2 DE19549155C2 DE19549155A DE19549155A DE19549155C2 DE 19549155 C2 DE19549155 C2 DE 19549155C2 DE 19549155 A DE19549155 A DE 19549155A DE 19549155 A DE19549155 A DE 19549155A DE 19549155 C2 DE19549155 C2 DE 19549155C2
- Authority
- DE
- Germany
- Prior art keywords
- layer
- oxide
- silicon substrate
- oxide layer
- nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 26
- 229910052710 silicon Inorganic materials 0.000 title claims description 26
- 239000010703 silicon Substances 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 title claims description 17
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 44
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940039095A KR0140655B1 (ko) | 1994-12-30 | 1994-12-30 | 반도체 장치의 소자 분리방법 |
| KR1019940039093A KR0167599B1 (ko) | 1994-12-30 | 1994-12-30 | 반도체 장치의 소자 분리방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE19549155A1 DE19549155A1 (de) | 1996-07-04 |
| DE19549155C2 true DE19549155C2 (de) | 2001-09-13 |
Family
ID=26630827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19549155A Expired - Fee Related DE19549155C2 (de) | 1994-12-30 | 1995-12-29 | Verfahren zum Isolieren von Halbleitereinrichtungen in einem Siliziumsubstrat |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5786229A (OSRAM) |
| JP (1) | JP2686735B2 (OSRAM) |
| CN (1) | CN1052113C (OSRAM) |
| DE (1) | DE19549155C2 (OSRAM) |
| TW (1) | TW290713B (OSRAM) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100261170B1 (ko) * | 1998-05-06 | 2000-07-01 | 김영환 | 반도체소자 및 그 제조방법 |
| US6071783A (en) * | 1998-08-13 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Pseudo silicon on insulator MOSFET device |
| US6881645B2 (en) * | 2000-08-17 | 2005-04-19 | Samsung Electronics Co., Ltd. | Method of preventing semiconductor layers from bending and semiconductor device formed thereby |
| US6649460B2 (en) | 2001-10-25 | 2003-11-18 | International Business Machines Corporation | Fabricating a substantially self-aligned MOSFET |
| US8673706B2 (en) * | 2004-09-01 | 2014-03-18 | Micron Technology, Inc. | Methods of forming layers comprising epitaxial silicon |
| US7132355B2 (en) * | 2004-09-01 | 2006-11-07 | Micron Technology, Inc. | Method of forming a layer comprising epitaxial silicon and a field effect transistor |
| KR101097469B1 (ko) * | 2009-07-31 | 2011-12-23 | 주식회사 하이닉스반도체 | 반도체 장치 및 그 제조방법 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4758531A (en) * | 1987-10-23 | 1988-07-19 | International Business Machines Corporation | Method of making defect free silicon islands using SEG |
| US5087586A (en) * | 1991-07-03 | 1992-02-11 | Micron Technology, Inc. | Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5108946A (en) * | 1989-05-19 | 1992-04-28 | Motorola, Inc. | Method of forming planar isolation regions |
| US4948456A (en) * | 1989-06-09 | 1990-08-14 | Delco Electronics Corporation | Confined lateral selective epitaxial growth |
| US5135884A (en) * | 1991-03-28 | 1992-08-04 | Sgs-Thomson Microelectronics, Inc. | Method of producing isoplanar isolated active regions |
-
1995
- 1995-12-20 JP JP7349078A patent/JP2686735B2/ja not_active Expired - Fee Related
- 1995-12-23 TW TW084113796A patent/TW290713B/zh active
- 1995-12-28 US US08/579,880 patent/US5786229A/en not_active Expired - Lifetime
- 1995-12-29 DE DE19549155A patent/DE19549155C2/de not_active Expired - Fee Related
- 1995-12-30 CN CN95118829A patent/CN1052113C/zh not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4758531A (en) * | 1987-10-23 | 1988-07-19 | International Business Machines Corporation | Method of making defect free silicon islands using SEG |
| US5087586A (en) * | 1991-07-03 | 1992-02-11 | Micron Technology, Inc. | Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer |
Also Published As
| Publication number | Publication date |
|---|---|
| US5786229A (en) | 1998-07-28 |
| CN1052113C (zh) | 2000-05-03 |
| DE19549155A1 (de) | 1996-07-04 |
| TW290713B (OSRAM) | 1996-11-11 |
| JPH08236611A (ja) | 1996-09-13 |
| JP2686735B2 (ja) | 1997-12-08 |
| CN1132411A (zh) | 1996-10-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8110 | Request for examination paragraph 44 | ||
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR |
|
| 8327 | Change in the person/name/address of the patent owner |
Owner name: MAGNACHIP SEMICONDUCTOR, LTD., CHEONGJU, KR |
|
| 8339 | Ceased/non-payment of the annual fee |