DE1591105A1 - Verfahren zum Herstellen von Festkoerperschaltungen - Google Patents

Verfahren zum Herstellen von Festkoerperschaltungen

Info

Publication number
DE1591105A1
DE1591105A1 DE19671591105 DE1591105A DE1591105A1 DE 1591105 A1 DE1591105 A1 DE 1591105A1 DE 19671591105 DE19671591105 DE 19671591105 DE 1591105 A DE1591105 A DE 1591105A DE 1591105 A1 DE1591105 A1 DE 1591105A1
Authority
DE
Germany
Prior art keywords
solid
state
interconnects
connections
state circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19671591105
Other languages
German (de)
English (en)
Inventor
Dipl-Phys Dr Hans Weinerth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Priority to DE19671591105 priority Critical patent/DE1591105A1/de
Priority to GB57772/68A priority patent/GB1212279A/en
Priority to FR1599169D priority patent/FR1599169A/fr
Publication of DE1591105A1 publication Critical patent/DE1591105A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips

Landscapes

  • Semiconductor Integrated Circuits (AREA)
DE19671591105 1967-12-06 1967-12-06 Verfahren zum Herstellen von Festkoerperschaltungen Pending DE1591105A1 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE19671591105 DE1591105A1 (de) 1967-12-06 1967-12-06 Verfahren zum Herstellen von Festkoerperschaltungen
GB57772/68A GB1212279A (en) 1967-12-06 1968-12-05 Method for the manufacture of microcircuits
FR1599169D FR1599169A (https=) 1967-12-06 1968-12-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19671591105 DE1591105A1 (de) 1967-12-06 1967-12-06 Verfahren zum Herstellen von Festkoerperschaltungen

Publications (1)

Publication Number Publication Date
DE1591105A1 true DE1591105A1 (de) 1970-09-24

Family

ID=5680111

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19671591105 Pending DE1591105A1 (de) 1967-12-06 1967-12-06 Verfahren zum Herstellen von Festkoerperschaltungen

Country Status (3)

Country Link
DE (1) DE1591105A1 (https=)
FR (1) FR1599169A (https=)
GB (1) GB1212279A (https=)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075945A3 (en) * 1981-09-30 1985-03-13 Kabushiki Kaisha Toshiba Stacked semiconductor device and method for manufacturing the device
WO1994007267A1 (en) * 1992-09-14 1994-03-31 Pierre Badehi Methods and apparatus for producing integrated circuit devices
EP0701284A1 (en) * 1994-09-06 1996-03-13 International Business Machines Corporation A semiconductor chip kerf clear method and resultant semiconductor chip and electronic module formed from the same
EP0708485A1 (en) * 1994-10-17 1996-04-24 International Business Machines Corporation Semiconductor chip and electronic module with integrated surface interconnects/components and fabrication methods therefor
US5716759A (en) * 1993-09-02 1998-02-10 Shellcase Ltd. Method and apparatus for producing integrated circuit devices
US6040235A (en) * 1994-01-17 2000-03-21 Shellcase Ltd. Methods and apparatus for producing integrated circuit devices
US6117707A (en) * 1994-07-13 2000-09-12 Shellcase Ltd. Methods of producing integrated circuit devices

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3235839A1 (de) * 1982-09-28 1984-03-29 Siemens AG, 1000 Berlin und 8000 München Halbleiterschaltung
JPS61288455A (ja) * 1985-06-17 1986-12-18 Fujitsu Ltd 多層半導体装置の製造方法
US12426228B2 (en) 2022-08-25 2025-09-23 International Business Machines Corporation SRAM with staggered stacked FET

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075945A3 (en) * 1981-09-30 1985-03-13 Kabushiki Kaisha Toshiba Stacked semiconductor device and method for manufacturing the device
WO1994007267A1 (en) * 1992-09-14 1994-03-31 Pierre Badehi Methods and apparatus for producing integrated circuit devices
US5455455A (en) * 1992-09-14 1995-10-03 Badehi; Peirre Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US5716759A (en) * 1993-09-02 1998-02-10 Shellcase Ltd. Method and apparatus for producing integrated circuit devices
US6040235A (en) * 1994-01-17 2000-03-21 Shellcase Ltd. Methods and apparatus for producing integrated circuit devices
US6117707A (en) * 1994-07-13 2000-09-12 Shellcase Ltd. Methods of producing integrated circuit devices
EP0701284A1 (en) * 1994-09-06 1996-03-13 International Business Machines Corporation A semiconductor chip kerf clear method and resultant semiconductor chip and electronic module formed from the same
EP0708485A1 (en) * 1994-10-17 1996-04-24 International Business Machines Corporation Semiconductor chip and electronic module with integrated surface interconnects/components and fabrication methods therefor

Also Published As

Publication number Publication date
FR1599169A (https=) 1970-07-15
GB1212279A (en) 1970-11-11

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