DE1305804T1 - Synchroner flash-speicher mit burst-status ausgabe - Google Patents

Synchroner flash-speicher mit burst-status ausgabe

Info

Publication number
DE1305804T1
DE1305804T1 DE1305804T DE01955000T DE1305804T1 DE 1305804 T1 DE1305804 T1 DE 1305804T1 DE 1305804 T DE1305804 T DE 1305804T DE 01955000 T DE01955000 T DE 01955000T DE 1305804 T1 DE1305804 T1 DE 1305804T1
Authority
DE
Germany
Prior art keywords
register
data
synchronous
memory device
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE1305804T
Other languages
German (de)
English (en)
Inventor
F. Roohparvar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24509337&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE1305804(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE1305804T1 publication Critical patent/DE1305804T1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
DE1305804T 2000-07-28 2001-07-27 Synchroner flash-speicher mit burst-status ausgabe Pending DE1305804T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/626,190 US6728798B1 (en) 2000-07-28 2000-07-28 Synchronous flash memory with status burst output
PCT/US2001/023695 WO2002011148A1 (en) 2000-07-28 2001-07-27 Synchronous flash memory with status burst output

Publications (1)

Publication Number Publication Date
DE1305804T1 true DE1305804T1 (de) 2003-11-27

Family

ID=24509337

Family Applications (2)

Application Number Title Priority Date Filing Date
DE1305804T Pending DE1305804T1 (de) 2000-07-28 2001-07-27 Synchroner flash-speicher mit burst-status ausgabe
DE60143700T Expired - Lifetime DE60143700D1 (cg-RX-API-DMAC7.html) 2000-07-28 2001-07-27

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE60143700T Expired - Lifetime DE60143700D1 (cg-RX-API-DMAC7.html) 2000-07-28 2001-07-27

Country Status (9)

Country Link
US (4) US6728798B1 (cg-RX-API-DMAC7.html)
EP (1) EP1305804B1 (cg-RX-API-DMAC7.html)
JP (1) JP3809909B2 (cg-RX-API-DMAC7.html)
KR (1) KR100511820B1 (cg-RX-API-DMAC7.html)
CN (2) CN101930794A (cg-RX-API-DMAC7.html)
AT (1) ATE492880T1 (cg-RX-API-DMAC7.html)
AU (1) AU2001277210A1 (cg-RX-API-DMAC7.html)
DE (2) DE1305804T1 (cg-RX-API-DMAC7.html)
WO (1) WO2002011148A1 (cg-RX-API-DMAC7.html)

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US7230876B2 (en) * 2005-02-14 2007-06-12 Qualcomm Incorporated Register read for volatile memory
US7640392B2 (en) 2005-06-23 2009-12-29 Qualcomm Incorporated Non-DRAM indicator and method of accessing data not stored in DRAM array
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US9262326B2 (en) * 2006-08-14 2016-02-16 Qualcomm Incorporated Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem
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US9741442B2 (en) * 2013-03-12 2017-08-22 Sandisk Technologies Llc System and method of reading data from memory concurrently with sending write data to the memory
US9430411B2 (en) * 2013-11-13 2016-08-30 Sandisk Technologies Llc Method and system for communicating with non-volatile memory
KR102164019B1 (ko) * 2014-01-27 2020-10-12 에스케이하이닉스 주식회사 버스트 랭스 제어 장치 및 이를 포함하는 반도체 장치
US9257165B2 (en) * 2014-03-10 2016-02-09 Everspin Technologies, Inc. Assisted local source line
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JP6420139B2 (ja) * 2014-12-26 2018-11-07 シナプティクス・ジャパン合同会社 半導体デバイス
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US11776591B2 (en) * 2019-09-26 2023-10-03 Arm Limited Concurrent access techniques utilizing wordlines with the same row address in single port memory
US11386937B2 (en) 2019-10-12 2022-07-12 Arm Limited System device and method for providing single port memory access in bitcell array by tracking dummy wordline
CN110955387B (zh) * 2019-10-25 2023-10-24 合肥沛睿微电子股份有限公司 自适应识别闪存类型方法及计算机可读取存储介质及装置
TWI780653B (zh) * 2019-11-08 2022-10-11 大陸商合肥沛睿微電子股份有限公司 識別快閃記憶體類型的方法及其裝置
TWI780654B (zh) * 2019-11-08 2022-10-11 大陸商合肥沛睿微電子股份有限公司 調整識別快閃記憶體類型的裝置及其方法
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Also Published As

Publication number Publication date
DE60143700D1 (cg-RX-API-DMAC7.html) 2011-02-03
US8010767B2 (en) 2011-08-30
CN101930794A (zh) 2010-12-29
ATE492880T1 (de) 2011-01-15
WO2002011148A1 (en) 2002-02-07
EP1305804B1 (en) 2010-12-22
JP3809909B2 (ja) 2006-08-16
EP1305804A1 (en) 2003-05-02
US20100088484A1 (en) 2010-04-08
US7603534B2 (en) 2009-10-13
US6728798B1 (en) 2004-04-27
AU2001277210A1 (en) 2002-02-13
US20040199713A1 (en) 2004-10-07
KR100511820B1 (ko) 2005-09-05
CN100578659C (zh) 2010-01-06
US7096283B2 (en) 2006-08-22
US20050289313A1 (en) 2005-12-29
JP2004505404A (ja) 2004-02-19
KR20030028556A (ko) 2003-04-08
CN1466762A (zh) 2004-01-07

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