WO2023009122A1

WO2023009122A1 - Minimize delay times for status checks to flash memory

Info

Publication number: WO2023009122A1
Application number: PCT/US2021/043682
Authority: WO
Inventors: Kang-Ning Feng; Ming-Chang HUNG; Heng-Fu CHANG
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2023-02-02

Abstract

An example device includes a flash memory and a controller. The controller is to vary delay times between sending commands to the flash memory and status checks to determine when the flash memory has completed implementing the commands. The controller is further to, when a single status check, following a respective delay time, results in the flash memory indicating that a respective command has been implemented, use the respective delay time in determining further delay times for later commands similar to the respective command.

Description

Minimize Delay Times for Status Checks To Flash Memory

BACKGROUND

[0001] Flash memories generally perform operations serially. Hence, commands to perform operations are generally provided to a flash memory serially. As such, when an external controller queries a flash memory to perform a status check on a command, the flash memory may temporarily suspend the operations to respond to the status check.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Reference will now be made, by way of example only, to the accompanying drawings in which:

[0003] Figure 1 is a block diagram of an example device to minimize delay times for status checks to a flash memory.

[0004] Figure 2 is a block diagram of another example device to minimize delay times for status checks to a flash memory.

[0005] Figure 3A depicts example 64 KB erase operations used to determine delay times that result in a single status check.

[0006] Figure 3B depicts example page program operations used to determine delay times that result in a single status check.

[0007] Figure 4 is an example of determining functions that relate cumulative delay times to respective numbers of operations.

[0008] Figure 5 is a flow diagram of an example method to minimize delay times for status checks to a flash memory.

[0009] Figure 6 is an example database storing functions that relate cumulative delay times to respective numbers of operations, as well as estimations of erase+program estimations and erase+program thresholds.

[0010] Figure 7 is an example of determining erase+program thresholds.

[0011] Figure 8 is a block diagram of another example device to minimize delay times for status checks to a flash memory.

[0012] Figure 9 is a flow diagram of another example method to minimize delay times for status checks to a flash memory.

DETAILED DESCRIPTION

[0013] Flash memories generally perform operations serially. Hence, commands to perform operations are generally provided to a flash memory serially. As such, when an external controller queries a flash memory to perform a status check on a command, the flash memory may temporarily suspend the operations to respond to the status check. Such status checks may hence delay the operations.

[0014] For example, when a device is erasing and/or writing data to a flash memory using, for example, erase commands, page program commands and/or write enable commands, a controller of the device sends a command to the flash memory to perform such operations. One flash memory transaction to perform erasing and writing data to a plurality of blocks of the flash memory may include many operations, and associated commands, for erasing and/or writing data to a flash memory. A controller at the flash memory, which may be referred to as a serial peripheral interface (SPI) controller, receives and implements the commands, for example by performing the commands serially. To confirm whether the command is completed, the controller may, after a delay time, transmit a request for a status check to the SPI controller which, when still performing the operation defined by the command, interrupts the operations to respond to the status check (e.g., in the negative and/or to indicate that the operations are not complete and/or that the flash memory is busy, and the like); such a process hence slows the operations from being performed.

[0015] Furthermore, delay times may vary by a model and/or manufacturer of a flash memory. For example, while a flash memory may store a “typical” delay time and/or a “maximum” delay time of an operation (e.g., and there may be different delay times for different operations), and such typical and/or maximum delay times may be accessed by a controller of the device in which a flash memory is installed to determine a delay time to use with an operation, such delay times are determined in a factory setting and/or an experimental setting under test conditions. As such, typical and/or maximum delay times provided with a flash memory may not represent actual delay times when installed in a laptop computer, a printer, and/or any other suitable device. For example, timing and/or duration for an operation may change with bus speed, operating voltage, physical layouts of circuits at the devices, and a host controller (e.g., the controller of the device in which the flash memory is installed) first-in-first-out (FIFO length), and life cycle of a memory cell in a flash memory.

[0016] Hence, provided herein is a device that includes a flash memory and a controller external to the flash memory. The controller may perform transactions to implement operations at the flash memory. In some examples, a transaction may be to update firmware stored at the flash memory, among other possibilities. A single transaction may include a plurality of operations, and an operation may include providing a command to the flash memory to perform the operation. The operations, and associated commands, may be of different types, such as to erase data at the flash memory, write data at the flash memory, and the like.

[0017] The controller varies delay times between sending commands to the flash memory and status checks to determine when the flash memory has completed implementing the commands. When a single status check, following a respective delay time, results in the flash memory indicating that a respective command has been implemented, the controller uses the respective delay time in determining further delay times for later commands similar to the respective command.

[0018] The flash memory is generally understood to be an electronic non volatile computer memory storage medium that may be electronically erased and reprogrammed. For example, the flash memory may be a s a distinct type of electrically erasable programmable read-only memory in which floating-gate transistors, and the like, is used to store data. The flash memory may be divided into a plurality of programmable segments. In one example, a programmable segment may be a sector or a page storing data of a size of 4 KB. Hereafter, the present specification will use the term “page” for a programmable segment, but it is understood that the term “page” may be replaced with the term “sector”. It is further understood that such a page (and/or sector) may be a minimum memory unit for the flash memory. In another example, a programmable segment may be a block storing data of a size of 64 KB, and one block may include data corresponding to 16 adjacent pages. Hence, in some examples, an operation for the flash memory may include the controller providing to the flash memory a command to erase a 4K programmable segment (e.g., 1 page), a command to erase a 32K programmable segment (e.g., 8 pages) or a command to erase a 64K programmable segment (e.g., 16 pages, or 1 block), which may respectively be referred to as a 4 KB erase command (and/or a single-page erase command), a 32 KB erase command (and/or a half-block erase command), and a 64 KB erase command (and/or a block erase command). In particular, when a block is 64 KB, a 64 KB erase command is understood to be a block erase command and a 32 KB erase command is understood to be a half-block erase command, however, block erase commands and half-block erase commands may be of other sizes depending on a size of a block.

[0019] However a command provided by the controller to the flash memory in an operation may be to write data to a page (e.g., and which is generally preceded by a command that erases data from the page), which may be referred to as a page program command. Furthermore, a command provided by the controller to the flash memory in an operation may be to place the flash memory into a write mode, which may be referred to as a write enable command.

[0020] The controller may provide any of these commands, in any suitable combination, to the flash memory, and/or may provide any other suitable commands to the flash memory. For example, erase commands may be combined with program commands to erase data from the flash memory at different pages, and write (e.g., program) data to the different pages. Such an erase/write combination may be referred to as an erase+program command cycle. Such an erase/write combination may further include a write enable command.

[0021] The controller may further vary delay times for different command types. For example, the controller may determine that different command types result in different delay times that result in a single status check from the flash memory indicating that a respective command has been implemented. For example, a delay time for a 64 KB erase command, that results in a single status check, may be longer than for a 4 KB erase command, that results in a single status check.

[0022] The controller may further correlate cumulative delay times for a plurality of operations associated with commands of a given type. For example, a transaction may include a plurality of operations that include commands of a given type, such as a plurality of 64 KB erase commands. The delay time for each operation, of the plurality of operations, may be the same, such that one delay time is used for the plurality of operations that include the commands of the given type. However, a delay time used in the plurality of operations that result in a single status check from the flash memory indicating that a respective command, of one of the operations, has been implemented, may be different for different numbers of the plurality of operations.

[0023] The controller may hence correlate a number of operations that use commands of a given type, with the cumulative duration of the operations (and/or the delay times of the commands of the operation) to generate a function and/or a model for determining durations of different numbers of operations and/or for selecting delay times for a given number of operations that include the commands of the given type. Such a correlation may comprise a linear regression which may be determined using a machine learning algorithm, and the like, trained to generate linear regression functions using a given “X” data (such as cumulative durations or cumulative delay times) and corresponding Ύ” data (such as corresponding numbers of operations), or vice versa.

[0024] The controller may further store the functions (e.g., at a memory and/or a database) and use the functions to determine durations for erase+program command cycles of different lengths to select an erase+program command cycle of a given length that results in a shortest duration for writing given data to the flash memory. For example, when 5 pages of data are to be written to the flash memory, and an erase+program command cycle that includes a 32 KB erase command and 8 page program commands (e.g., that respectively erases 8 pages, and writes data to the 8 pages) has a shorter duration than 54 KB and/or single-page erase commands, and 5 page program commands (e.g., that respectively erases 5 pages, and writes data to the 5 pages), the erase+program command cycle that includes a 32 KB erase command is selected to writing the 5 pages of data to the flash memory.

[0025] An aspect of the specification provides a device comprising: a flash memory; and a controller to: vary delay times between sending commands to the flash memory and status checks to determine when the flash memory has completed implementing the commands; and when a single status check, following a respective delay time, results in the flash memory indicating that a respective command has been implemented, use the respective delay time in determining further delay times for later commands similar to the respective command.

[0026] Another aspect of the specification provides a method comprising: generating, at a controller of a device that includes a flash memory, functions that relate a number of operations, associated with commands of respective given types, to associated cumulative delay times of the operations that result in a single status check, the commands to perform the operations at the flash memory; using, at the controller, the functions used to determine durations for erase+program command cycles of different lengths; and selecting, at the controller, an erase+program command cycle of a given length that results in a shortest duration for writing given data to the flash memory.

[0027] Another aspect of the specification provides a non-transitory computer- readable medium comprising instructions executable by a controller to: maintain a database of functions that relate a number of operations, associated with commands of respective given types, to associated cumulative delay times of the operations that result in a single status check, the commands to perform the operations at a flash memory; use the functions used to determine durations for erase+program command cycles of different lengths, the durations maintained at the database; use the functions used to determine thresholds for selecting the erase+program command cycles of different lengths, the thresholds maintained at the database; and select, using the thresholds and the durations, an erase+program command cycle of a given length that results in a shortest duration for writing given data to the flash memory.

[0028] Referring to Figure 1 , a device 100 to minimize delay times for status checks to a flash memory is provided. The device 100 comprises a controller 102 and a flash memory 104.

[0029] The device 100 may include, but is not limited to, a computing device, a mobile phone, a smart phone, a desktop computer, an all-in-one (AIO) computer, a laptop computer, a peripheral device, a printer, a scanner, and the like, and/or any other suitable device and/or electronic device that may incorporate the flash memory 104.

[0030] The controller 102 may include a central processing unit (CPU), a graphics processing unit (GPU) a microcontroller, a microprocessor, a processing core, a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), and the like. While not depicted, the device 100 may further comprise a memory (e.g., a random access memory (RAM) and/or a read only memory (ROM), such a memory may be different from the flash memory 104, or the flash memory 104 may be a component of such a memory. Furthermore, such a memory may store instructions which, when executed by the controller 102, cause the controller 102 to implement functionality described herein. Regardless, such a memory may store a database, and the like, of functions described herein.

[0031] The flash memory 104 may comprise a flash read-only memory (ROM) that may store firmware of the device 100 (e.g., device firmware) and/or any other suitable data. However, the flash memory 104 is understood to be capable of being erased and re-programmed. In particular examples, the flash memory 104 may be erased and re-programmed when the device firmware is to be updated with a firmware update, and the like. However, any suitable data may be stored at the flash memory 104. Further, the flash memory 104 may be NOR- based. Examples of the device firmware include, but are not limited to, basic input/output system (BIOS), Unified Extensible Firmware Interface (UEFI) specification, and computer programs for operating systems for computing device, printers, and other electronic devices (e.g., depending on a type of the device 100). While not depicted, the flash memory 104 is understood to include an SPI controller to implement commands from the controller 102.

[0032] For example, as previously described, the controller 102 may be generally to implement operations to erase and/or write data using commands provided to the flash memory 104 which generally performs such operations serially. Indeed, an operation, and associated command, may represent one operation of a transaction that includes a plurality of operations.

[0033] The controller 102 may provide a command to the flash memory 104 and, after a delay time, request a status check on the command. If the delay time is shorter than a time for the flash memory 104 to implement the operation, the flash memory 104 interrupts the implementation of the operation to respond to the status check with an indication that the operation is not complete and/or the flash memory 104 is busy, and the like, which delays implementation of the operation (e.g., see example operations 300, 350 of Figure 3Aand Figure 3B, described herein). Furthermore, as the controller 102 generally won’t send another operation and/or command to the flash memory 104 until the flash memory 104 indicates that a previous operation and/or command is completed (e.g., and which may be requirement of the flash memory 104), when a status check is not successful (e.g., the flash memory 104 responds to the status check with an indication that the operation is not complete), the controller 102 will generally request another status check after another delay time. Depending on how many status checks occur until the operation is complete, a time to implement an operation at the flash memory 104 may be increased relative to when one status check results in the flash memory 104 indicating that a respective command and/or operation has been implemented.

[0034] As such, the controller 102 is generally to: vary delay times between sending commands to the flash memory 104 and status checks to determine when the flash memory 104 has completed implementing the commands; and when a single status check, following a respective delay time, results in the flash memory 104 indicating that a respective command has been implemented, use the respective delay time in determining further delay times for later commands similar to the respective command. [0035] Put another way, the controller 102 determines a delay time for a command and/or operation of a given type that results in a single status check indicating that the command and/or operation has been implemented, and uses this delay time to determine delay times for later commands of the give type. [0036] Such commands may include, but are not limited to: block erase commands; single-page erase commands; 4 KB erase commands; half-block erase commands; 32 KB erase commands; block erase commands; 64 KB erase commands; page program commands; write enable commands; ora combination.

[0037] The controller 102 may vary the delays times by selecting the delay times, for respective command types, based on: a predetermined typical delay time associated with the flash memory 104; a predetermined maximum delay time associated with the flash memory 104; or, a combination. In particular, for a given command type, the flash memory may store (e.g., at dedicated pages), predetermined typical delay times and/or predetermined maximum delay times for commands of different types. The controller 102 may retrieve such predetermined typical delay times and/or predetermined maximum delay times from the flash memory 104. The controller 102 may initially select a delay time for a command of a given type to be between an associated predetermined typical delay time and an associated predetermined maximum delay time. Alternatively, the controller 102 may initially select a delay time for a command of a given type to be within a given percentage of an associated predetermined typical delay time, such as 5%, 10%, 20%, among other possibilities, and furthermore the initially selected delay time may be less then (e.g., by the given percentage) or more than (e.g., by the given percentage) the associated predetermined typical delay time.

[0038] When the initially selected delay time, for an operation that includes a command of the given type, results in a response to a status check, from the flash memory 103, of an indication that the operation is not complete and/or the flash memory 104 is busy, and the like, a next time an operation that includes the command of the given type is used, the controller 102 increases a duration of a delay time prior to a status check. However, when the initially selected delay time, for an operation that includes a command of the given type, results in a response to a status check, from the flash memory 103, of an indication that the operation is complete, and the like, a next time an operation that includes the command of the given type is used, the controller 102 may decrease a duration of a delay time prior to a status check. Such changes in duration may occur until a smallest delay time is found that results in a single status check indicating that a respective command has been implemented. Delay times may be increased or decreased according to any suitable scheme including, increasing, or decreasing, delay times by a given percentage, such as 5%, 10%, 20%, among other possibilities.

[0039] As has been previously discussed, a transaction may include a plurality of operations of a given type, such as a plurality of 64 KB erase commands, to erase different blocks of the flash memory 104, and that may be provided to the flash memory 104 serially in conjunction with page program commands to write data to respective pages of the different blocks of the flash memory 104. In these examples, for a given set of operations of a given type, the controller 102 may initially use a same delay time, and increase, or decrease, the delay times for subsequent sets of operations of the given type. Alternatively, the controller 102 may increase, or decrease, the delay times while implementing a given set of operations of a given type.

[0040] Regardless, the controller 102 may generally collect indications of the delay times, for respective command types, that result in the flash memory 104 indicating that the respective command types have been implemented after single status checks; such indications may include a length of such delay times, which may be designated as “Valid”. In contrast, the controller 102 may generally discard other indications of the delay times that result in the flash memory 104 indicating that the respective command types have been implemented using more than one status check; put another way, such delay times may be designated as “Invalid”. In this manner, the controller 102 may collect information on delay times that result in the flash memory 104 indicating that respective command types have been implemented using a single status check, and use this information to determine later delays times for the respective command types.

[0041] For example, after a given period of time (e.g., 1 hour, 1 day, or any other suitable period of time) or a given number of commands of a given type resulted in single status checks (e.g., such as 500, 1000, 2000, or any other suitable number) the controller 102 may generate a function, using the indications of valid delay times, that relates a number of operations, associated with commands of the given type, to associated cumulative durations and/or delay times of the operations; and use the function to determine further durations and/or delay times for later commands of the given type.

[0042] For example, such a function may be determined using linear regression and/or using a machine learning algorithm that performs linear regressions. In such examples, a linear relationship may be determined between a number of operations of a given type and cumulative delay times thereof.

[0043] Hence, when a transaction includes a plurality of operations of a given type, such as given number of 64 KB erase commands, an associated function may be used to determine a delay time, using the given number and/or a duration of the given number of 64 KB erase commands. For example, such a function may output, using the given number, a cumulative delay time for the given number, and the delay time to use for the given number of 64 KB erase commands may be the cumulative delay time divided by the given number; and/or such a function may output, using the given number, a cumulative duration time for the given number which may be used to estimate durations of operations that include the given number (e.g., as described below with respect to Figure 5, Figure 6 and Figure 7).

[0044] Attention is next directed to Figure 2, which depicts another example device 200 to minimize delay times for status checks to a flash memory. The device 200 is substantially similar to the device 100, with like components having like numbers, but in a “200” series” rather than a “100” series. Hence, as depicted, the device 200 comprises a controller 202, substantially similar to the controller 102, and a flash memory 204, substantially similar to the flash memory 104.

[0045] As depicted, the device 200 further comprises a memory 206, coupled to the controller 202 and includes a non-transitory machine-readable storage medium that may be any electronic, magnetic, optical, or other physical storage device. The non-transitory machine-readable storage medium of the memory 206 may include, for example, random access memory (RAM), electrically- erasable programmable read-only memory (EEPROM), flash memory (e.g., the flash memory 204, or another flash memory), a storage drive, an optical disc, and the like. The memory 206 may also be encoded with executable instructions 208 to minimize delay times for status checks to the flash memory 204.

[0046] The instructions 208 may include, but are is not limited to, a machine learning algorithm that has been trained to perform linear regressions and/or to generate functions that relate a number of operations, associated with commands of respective given types, to associated cumulative delay times of the operations that result in a single status check and/or to associated cumulative durations that include delay times that result in a single status check. [0047] Furthermore, the flash memory 204 may be a component of the memory 206.

[0048] The memory 206 may also store an operating system that is executable by the controller 102 to provide general functionality to the device 100, for example, functionality to support various applications such as a user interface to access various features of the device 100. Examples of operating systems include a Real-Time Operating System (RTOS). Windows™, macOS™, iOS™, Android™, Linux™, and Unix™. However, such an operating system, and/ora portion thereof, may be stored at the flash memory 204.

[0049] The memory 206 may additionally store applications that are executable by the controller 202 to provide specific functionality to the device 200, such as those described in greater detail below and which may include the instructions 208. Regardless, the controller 202 and the memory 206 may cooperate to execute various instructions, such as the instructions 208.

[0050] As depicted, the memory 206 further stores a database 210 of functions that relate a number of operations, associated with commands of respective given types, to associated cumulative delay times of the operations that result in a single status check, the commands to perform the operations at the flash memory 204. The database 210, and the functions, are described in more detail below with respect to Figure 6, however it is understood that the database 210 may store other data including, but not limited to, durations for erase+program command cycles of different lengths, thresholds for selecting the erase+program command cycles of different lengths, the functions generated at different times to track aging of the flash memory 204, or a combination, among other possibilities. It is further understood that the controller 202 maintains the database 210.

[0051] Details of the flash memory 204 are also depicted. In particular, the flash memory 204 includes an SPI controller 212 and a plurality of blocks, of which one example block 214 is depicted. The SPI controller 212 is understood to implement commands received from the controller 202 (and which may also be referred to as the host controller 202). The SPI controller 212 is further understood to respond to status checks received from the host controller 202. Hence, for example, when the flash memory 204 is described hereafter as implementing a command and/or responding to a status check, and/or performing any other suitable functionality, it is understood that the SPI controller 212 is implementing such functionality.

[0052] As depicted, the block 214 comprises sixteen (e.g., 16) pages 216 (e.g., of 4 KB, fora total of 64 KB), numbered 1 to 16, each of which include data respectively labeled “Datal”, “Data2”...”Data16”. Data stored in a page 216 may include any suitable data, including, but not limited to, null data, data related to firmware for the device 200 and/or hashes of data of the firmware (e.g., which may be compared to hashes representing firmware updates to determine whether or not to update data of the firmware).

[0053] However, in other examples, pages 216 may be larger or lower than 4 KB and/or blocks 214 maybe larger or lower than 64 KB. For example, blocks herein may be 32 KB (e.g., half a block 214 as presently described) 128 KB,

256 KB, or 512 KB, among other possibilities, and pages of such blocks may be 4 KB, or higher than 4 KB (or lower than 4 KB). In some of these examples, a size of a block may correspond to a size of a maximum supported erase command/ For example, a flash memory that includes 128 KB blocks may support a 128 KB erase command (e.g., a block erase command) and/or a 128 KB erase+program command cycle (e.g., a block+program command cycle), as well as a 64 KB erase command (e.g., a half-block erase command) and/or a 64 KB erase+program command cycle (e.g., a half-block+program command cycle). Other block erase commands and/or half-block erase commands of any other suitable size are within the scope of the present specification.

[0054] While only one block 214 is depicted, it is understood that the flash memory 204 may include any suitable number of blocks 214. For example, the flash memory 204 may comprise a 1 GB flash memory, a 4GB flash memory, and/or another suitably sized flash memory, with a corresponding number of blocks 214 and pages 216.

[0055] As depicted, the flash memory 204 further stores (e.g., at another block 214 and/or at dedicated pages of the flash memory 204), data 218 that indicate factory specifications of the flash memory 204; as depicted, such data 218 includes maximum delay times and typical delay times for commands of given type, the data 218 being predetermined and stored at the flash memory 204 at a factory, and the like. For example, maximum delay times and typical delay times may be different for 4 KB erase commands, 32 KB erase commands, 64 KB erase commands, page program commands, and hence the data 218 may include respective maximum delay times and respective typical delay times for the different commands.

[0056] In general, the device 200 is configured to implement similar functionality as that described with respect to the device 100, which is next described in more detail.

[0057] For example, attention is next directed to Figure 3A which depicts examples of 64 KB erase operations that may be implemented by the controller 202 communicating with the flash memory 204. It is understood in Figure 3A that the operations occur over time, which is indicated on a “Time” axis; hence a duration to perform a particular component of an operation of Figure 3A is understood to be represented by a length thereof along the Time axis.

[0058] As depicted, for example, a 64 KB erase operation 300 includes providing a 64 KB erase command to the flash memory 204, waiting a first delay time (e.g., a duration thereof indicated by its length along the time axis), and requesting a first status check. It is assumed in this example that the SPI controller 212 responds to the first status check with an indication that the 64 KB erase command has not yet been completed. Hence, after waiting a second delay time (which, as depicted, may be of the same duration as the first delay time), a second status check is requested. It is assumed in this example that the SPI controller 212 responds to the second status check with an indication that the 64 KB erase command has been completed. However, as two status checks were used, the operation 300 is considered to be “Invalid” by the controller 202 as the duration of the first delay time and the second delay time resulted in two status checks and not a single status check. Furthermore, it is understood that operation 300 may represent a prior art implementation of status checks for 64 KB erase operations and/or other erase operations.

[0059] Hence, a next time a 64 KB erase operation 302 occurs, the controller 202 may lengthen a delay time between a 64 KB erase command and a status check, relative to the delay times of the operation 300. Indeed, for the operation 302, it is assumed that the SPI controller 212 responds to the single status check with an indication that the 64 KB erase command has been completed. Hence the operation 302 is considered to be “Valid” by the controller 202 and the delay time may be stored and/or used to determine a cumulative delay time of a plurality of related 64 KB erase operations (e.g., of a given transaction). [0060] In some examples, a next time a 64 KB erase operation 304 occurs, the controller 202 may shorten a delay time between a 64 KB erase command and a status check relative to the delay time of the operation 302, but which is still longer than the delay times of the operation 300. Indeed, for the operation 304, it is assumed that the SPI controller 212 responds to the single status check with an indication that the 64 KB erase command has been completed. Hence the operation 304 is considered to be “Valid” by the controller 202 and the delay time may be stored and/or used to determine a cumulative delay time of a plurality of related 64 KB erase operations (e.g., of a given transaction).

[0061] Furthermore, while the durations of the commands and the status checks are all depicted as being respectively the same and/or similar, such durations may also vary depending on the conditions at the device 200 (e.g., that may affect the delay times).

[0062] Furthermore, durations of the operations 302, 304 (e.g., distance along the time axis), and/or respective delay times, may be measured by the controller 202 and which may be used to generate functions described below with respect to Figure 4.

[0063] Figure 3Aalso shows durations (e.g., distance along the time axis) of 64 KB erase operations 306, 308 if the typical delay time, or the maximum delay time (e.g., from the data 218), were respectively used. Indeed, the initial delay times of the operation 300 may be selected based on a given percentage of the typical delay time and/or the initial delay times of the operation 300 may be selected to be between the and the maximum delay time.

[0064] It is furthermore understood that the examples of Figure 3A may be applied to other types of erase operations, such as 4 KB erase operations, 32 KB erase operations, and the like, but with different delay times.

[0065] Attention is next directed to Figure 3B which is similar to Figure 3A, but depicts page program operations. As depicted, for example, a page program operation 350 includes providing a page program command to the flash memory 204, as well as data to be written to a given page, waiting a first delay time (e.g., a duration thereof indicated by its length along the time axis), and requesting a first status check. It is assumed in this example that the SPI controller 212 responds to the first status check with an indication that the page program command has not yet been completed. Hence, after waiting a second delay time (which, as depicted, may be of the same duration as the first delay time), a second status check is requested. It is assumed in this example that the SPI controller 212 responds to the second status check with an indication that the page program command has been completed. However, as two status checks were used, the operation 350 is considered to be “Invalid” by the controller 202 as the duration of the first delay time and the second delay time resulted in two status checks and not a single status check. Furthermore, it is understood that operation 350 may represent a prior art implementation of status checks for page program operations. [0066] Hence, a next time a page program operation 352 occurs, the controller 202 may lengthen a delay time between page program command and a status check, relative to the delay times of the operation 350. Indeed, for the operation 352, it is assumed that the SPI controller 212 responds to the single status check with an indication that the page program command has been completed. Hence the operation 352 is considered to be “Valid” by the controller 202 and the delay time may be stored and/or used to determine a cumulative delay time of a plurality of related page program operations (e.g., of a given transaction). [0067] Furthermore, durations of the operation 352 (e.g., distance along the time axis), and/or respective delay times, may be measured by the controller 202 and which may be used to generate functions described below with respect to Figure 4.

[0068] Figure 3B also shows durations of page program operations 356, 358 (e.g., distance along the time axis) of the typical delay time, or the maximum delay time (e.g., from the data 218), were respectively used. Indeed, the initial delay times of the operation 350 may be selected based on a given percentage of the typical delay time and/or the initial delay times of the operation 350 may be selected to be between the and the maximum delay time.

[0069] Attention is next directed to Figure 4 which depicts a graphic illustration of a determination of a function for operations and/or commands of a given type. [0070] In particular, Figure 4 depicts a graph 400 in which cumulative delay times for implementing respective numbers of operations of a given type (e.g., 64 KB erase operations) are plotted against the respective numbers of operations.

[0071] For example, data points 402 may represent a cumulative duration for performing an associated given number of operations. For example one data point 402 may represent a cumulative duration for implementing one hundred (e.g., 100) operations of a given type for one transaction, while another data point 402 may represent a cumulative duration for five hundred (e.g., 500) operations of the same given type for another transaction, etc. A data point 402 may be referred to as being a measurement of a cumulative duration for operations of a given type for a transaction (e.g., the measurements described with respect to Figure 3A and Figure 3B, but for one, or more than one, operation). Alternatively, the data points 402 may represent a cumulative delay time for performing an associated given number of operations. However, hereafter, examples are provided which use the cumulative duration.

[0072] For example, a cumulative duration may include durations for providing a command, a single delay time, and a status check per command. As such, a function, which may be determined from the data points 402, may relate a number of operations, associated with commands of respective given types, to associated cumulative times of the operations (e.g., that include the associated cumulative delay times). Alternatively, a function which may be determined from the data points 402 relates a number of operations to associated cumulative delay times of the operations. However, hereafter functions for cumulative durations of operations are described.

[0073] Regardless, for such measurements, for a set of a given number of operations, a delay time may have been varied for the set until a single status check resulted in the flash memory 204 indicating that a respective command had been implemented for an operation in the set, but invalid measurements were discarded. Put another way, the data points 402 represent cumulative “Valid” operations and/or delay times but not “Invalid” operations and/or delay times. As such, functions described herein may be referred to as functions that relate a number of operations, associated with commands of respective given types, to associated cumulative durations that included delay times of the operations that result in a single status check; and/or functions described herein may be referred to as functions that relate a number of operations, associated with commands of respective given types, to associated cumulative delay times of the operations that result in a single status check.

[0074] As also depicted in Figure 4, the controller 202 is understood to use the data points 402 to perform a linear regression (e.g., using a machine learning algorithm of the instructions 208, for example) to generate a function represented by the line 404 (and is hence labelled “Regression”). Such a function may have a format of “y=mx+b” where “m” and “b” represent a slope and intercept of the line 404. Hence once “m” and “b” are determined, for a given number of operations (e.g., “y”), an associated cumulative duration (e.g., “x”) may be determined. However, the function may be adapted such that for a given number of operations, a given duration and/or a single delay time for a single operation may be determined, which may represent an average duration and/or an average delay time for the operations of the given type represented by the function.

[0075] It is further understood that, when a given number of operations of a given type are to be implemented in a transaction, the function represented by the line 404 may be used to select a delay time for the operations. For example, when an integer number “P” of 64 KB erase commands are to be used, the integer number “P” may be input to the function to determine an associated cumulative duration of the “P” number of 64 KB erase commands, and/or an associated cumulative delay time. In particular, when the associated cumulative duration is determined, an average delay time of one 64 KB command may be determined by dividing the associated cumulative duration by “P” and subtracting predetermined and/or measured durations for transmitting a 64 KB command and providing (and receiving a response to) to a status check; in other words, in these examples, the controller 202 may further measure respective durations for transmitting a 64 KB command and providing (and receiving a response to ) to a status check. However, when an associated cumulative delay time is determined, an average delay time of one 64 KB command may be determined by dividing the associated cumulative delay time by “P”.

[0076] Also depicted in Figure 4 is a line 406 which represents cumulative durations (and/or cumulative delay times) for the operations if a respective typical delay time from the data 218 had been used. Similarly, also depicted in Figure 4, is a line 408 which represents cumulative durations (and/or cumulative delay times) for the operations if a respective maximum delay time from the data 218 had been used. As is apparent from Figure 4, comparing the lines 404, 406, delay times represented by the line 404 are (e.g., on average) less than the typical delay time.

[0077] Referring to Figure 5, a flowchart of an example method 500 to minimize delay times for status checks to a flash memory is depicted. In order to assist in the explanation of method 500, it will be assumed that the method 500 may be performed at least partially by the device 200, and/or the controller 202 thereof, implementing the method 500 for example by executing the instructions 208. Indeed, the method 500 may be one way in which the device 200 may be configured. Furthermore, the following discussion of method 500 may lead to a further understanding of the device 200, and its various components. Furthermore, it is to be emphasized, that method 500 may not be performed in the exact sequence as shown, and various blocks may be performed in parallel rather than in sequence, or in a different sequence altogether. Furthermore, the method 500 may be performed at the device 100.

[0078] At a block 502, the device 200 and/or the controller 202 generates (e.g., at the device 200 which includes the flash memory 204), functions that relate a number of operations, associated with commands of respective given types, to associated cumulative delay times of the operations that result in a single status check, the commands to perform the operations at the flash memory 204.

[0079] For example, as has already been described with respect to Figure 4, generating the functions may comprise: using a machine learning algorithm to generate the functions, generating linear regressions of the number of operations and the associated cumulative delay times, or a combination.

Indeed, while use of a machine learning algorithm may be fastest at determining linear regressions, any suitable process for generating the linear regressions, or another suitable function, is within the scope of the present specification.

[0080] Furthermore, while present examples are described with respect to linear regressions, other types of functions are within the scope of the present specification. For example, parabolic functions may alternatively be used, among other possibilities.

[0081] In particular, the controller 202 and/or the device 200 may generate a 64 KB erase function, a 32 KB erase function, a 4 KB erase function, and a page program function. While not depicted, in some examples, the controller 202 and/or the device 200 may generate a write enable function. For simplicity, it is assumed hereafter that the functions provide a duration to perform an entire command (including a duration for providing a command, a delay time, and a single status check).

[0082] It is further understood that such functions may be stored at the memory 206, such as at the database 210.

[0083] At a block 504, the device 200 and/or the controller 202 uses the functions used to determine durations for erase+program command cycles of different lengths, which may also be stored at the database 210.

[0084] For example, an erase+program command cycle may include one erase command that erases a given number of pages, as well as page program commands of the same given number. Hence, a 64 KB erase+program command cycle (e.g., a block erase+program command cycle) may include one 64 KB erase command, to erase 16 pages and/or 1 block, and 16 page program commands to write data to the 16 pages which were erased. Similarly, a 32 KB erase+program command cycle (e.g., a half-block erase+program command cycle) may include one 32 KB erase command, to erase 8 pages of a block, and 8 page program commands to write data to the 8 pages which were erased. Similarly, a 4 KB erase+program command cycle e.g., a page erase+program command cycle) may include one 4 KB erase command, to erase 1 page of a block, and 1 page program commands to write data to the 1 page which was erased.

[0085] As such, at the block 504, using a 64 KB erase+program command cycle as an example, the device 200 and/or the controller 202 may use the 64 KB erase function to determine a first duration to implement one 64 KB erase command, and the device 200 and/or the controller 202 may use the page program function to determine a second duration to implement 16 page program commands. As such, a total duration for a 64 KB erase+program command cycle (e.g., a block erase+program command cycle) may be determined by adding the first duration to the second duration. Such a total duration may be stored at the database as a 64 KB erase+program estimation (e.g., a block+program estimation) of the total duration.

[0086] Similarly, using a 32 KB erase+program command cycle (e.g., a half block erase+program command cycle) as an example, the device 200 and/or the controller 202 may use the 32 KB erase function to determine a first duration to implement one 32 KB erase command, and the device 200 and/or the controller 202 may use the page program function to determine a second duration to implement 8 page program commands. As such, a total duration for a 32 KB erase+program command cycle may be determined by adding the first duration to the second duration. Such a total duration may be stored at the database as a 32 KB erase+program estimation (e.g., a half-block+program estimation) of the total duration.

[0087] Similarly, using a 4 KB erase+program command cycle e.g., a page erase+program command cycle) as an example, the device 200 and/or the controller 202 may use the 4 KB erase function to determine a first duration to implement one 4 KB erase command, and the device 200 and/or the controller 202 may use the page program function to determine a second duration to implement 1 page program command. As such, a total duration for a 4 KB erase+program command cycle may be determined by adding the first duration to the second duration. Such a total duration may be stored at the database as a 4 KB erase+program estimation (e.g., a page+program estimation) of the total duration.

[0088] At a block 506, the device 200 and/or the controller 202 selects an erase+program command cycle of a given length that results in a shortest duration for writing given data to the flash memory 204.

[0089] For example, the device 200 and/or the controller 202 may determine that given data (e.g., of a device firmware update) is to be written to a given block 214, and that the given data is 5 pages. As such the device 200 and/or the controller 202 may determine whether five 4 KB erase+program command cycles has a longer or shorter duration than one 32 KB erase+program command cycle (and/or one 64 KB erase+program command cycle). Such a determination may occur by adding five 4 KB erase+program estimations to determine a total duration for five 4 KB erase+program command cycles, and comparing to the 32 KB erase+program estimation. When the total duration for the five 4 KB erase+program command cycles is shorter than the 32 KB erase+program estimation, then five 4 KB erase+program command cycles are used to write the 5 pages of given data to the flash memory 204. However, when the total duration for the five 4 KB erase+program command cycles is longer than the 32 KB erase+program estimation, then the 32 KB erase+program command cycle is used to write the 5 pages of given data to the flash memory 204.

[0090] It is understood, in these examples, that while the 5 pages to be written to the flash memory 204 may not be consecutive, they are all within 8 consecutive pages 216 of a block 214 (e.g., as a 32 KB erase command generally erases 8 consecutive pages 216 of a block 214) and in particular a first 8 pages 216 ora last 8 pages 216 (e.g., of the 16 pages).

[0091] Indeed, similarly understood that when the 5 pages to be written to the flash memory 204 may not be consecutive, they are not within 8 consecutive pages 216 of a block 214, but are within 16 consecutive pages 216 of a block 214, a 64kb erase command may be used.

[0092] A similar comparison may occur for any given data that is to be written to the flash memory 204 of any given number of pages, and furthermore, such a comparison may be between 4 KB erase+program command cycles and a 32 KB erase+program command cycle, and/or such a comparison may be between 4 KB erase+program command cycles and a 64 KB erase+program command cycle, and/or such a comparison may be between 32 KB erase+program command cycles and a 64 KB erase+program command cycle.

[0093] Put another way, selecting an erase+program command cycle of a given length that results in a shortest duration for writing given data to the flash memory 204 may comprise: when a larger block erase command, and corresponding program commands, has a duration for writing the given data to the flash memory 204 that is less than a respective duration of a combination of shorter single-page erase commands, and respective corresponding program commands, for writing the given data to the flash memory 104, the device 200 and/or the controller 202 may use the larger block erase command, and the corresponding program commands, to write the given data to the flash memory 204.

[0094] Alternatively threshold may be used to select an erase+program command cycle of a given length that results in a shortest duration for writing given data to the flash memory 204.

[0095] For example, the device 200 and/or the controller 202 may determine, from the 4 KB erase+program estimation and the 32 KB erase+program estimation, a smallest number of the 4 KB erase+program command cycles that has a longer duration than a 32 KB erase+program command cycle. Such a number may be stored as a 32 KB erase+program threshold, and/or a 32 KB erase+program threshold may be stored as the duration of such a number of 4 KB erase+program command cycles. It is further understood that such a number corresponds to a number of pages at the flash memory 204 (e.g., as one 4 KB erase+program writes data to one page).

[0096] Hence, when given data of a given number of pages is to be written to the flash memory 204, the device 200 and/or the controller 202 may determine the given number of pages of the given data and compare to a number of pages of the 32 KB erase+program threshold. When the given number of pages of the given data is less than the number of pages of the 32 KB erase+program threshold, then the given number of 4 KB erase+program command cycles may be used to write the given data to the flash memory 204. Alternatively, when the given number of pages of the given data is equal to, or greater than, than the number of pages of the 32 KB erase+program threshold, then a 32 KB erase+program command cycle may be used to write the given data to the flash memory 204.

[0097] Similarly, a 64 KB erase+program threshold may also be determined which may comprise a smallest number of the 4 KB erase+program command cycles that has a longer duration than a 64 KB erase+program command cycle. Hence, when a given number of pages of given data to be written to the flash memory 204 is less than the number of pages of the 64 KB erase+program threshold (e.g., and greater than the number of pages of the 32 KB erase+program threshold), then either the given number of 4 KB erase+program command cycles may be used to write the given data to the flash memory 204, ora combination of 4 KB erase+program command cycles and a 32 KB erase+program command cycle may be used to write the given data to the flash memory 204, whichever has the shortest duration. Alternatively, when the given number of pages of the given data is equal to, or greater than, than the number of pages of the 64 KB erase+program threshold, then a 64 KB erase+program command cycle may be used to write the given data to the flash memory 204. [0098] Indeed, the device 200 and/or the controller 202 may determine, using the various thresholds, any suitable combination of the erase+program command cycles that has a shortest duration to write given data to the flash memory 204.

[0099] Put another way, using the functions used to determine durations for the erase+program command cycles of different lengths may comprise: using the functions to determine thresholds for selecting erase+program command cycles of different given lengths, and the thresholds may be time based, memory-size based, page number based, or a combination.

[00100] Furthermore, while present examples are described with respect to 4 KB, 32 KB and 64 KB commands, it is understood that the method 500 may further comprise the device 200 and/or the controller 202 determining a single page erase+program command cycle duration (e.g., which may comprise a 4 KB erase+program command cycle duration, or single page erase+program command cycle durations of any suitable size); and using the single-page erase+program command cycle duration to determine the thresholds for using block erase+program command cycles (e.g., which may comprise a 32 KB erase+program command cycle duration, ora 64 KB erase+program command cycle duration, or block page erase+program command cycle durations of any suitable size).

[00101] As such, the method may further comprise, the device 200 and/or the controller 202: when a combination of shorter single-page erase commands, and respective corresponding program commands, for writing the given data to the flash memory 204, has a duration that is greater than a threshold for using a block erase+program command, using the block erase+program command to write the given data to the flash memory 204.

[00102] Similarly, the method may further comprise, the device 200 and/or the controller 202: when a combination of shorter single-page erase commands, and respective corresponding program commands, for writing the given data to the flash memory 204, has a duration that is less than a threshold for using a block erase+program command, using the combination of the shorter single page erase commands, and respective corresponding program commands to write the given data to the flash memory 204.

[00103] As has been previously mentioned data stored in a page 216 and/or block 214of the flash memory 204 may include any suitable data, including, but not limited to, null data, data related to firmware for the device 200 and/or hashes of data of the firmware (e.g., which may be compared to hashes representing firmware updates to determine whether or not to update data of the firmware). Hence, similarly, given data that is to be written to the flash memory 204 may include, but is not limited to, data related to firmware for the device 200 and/or hashes of data of the firmware. Hence, in some examples, an erase- program cycle is to store hash data at the flash memory 204, for example to update hash data already stored at the flash memory 204, the updated hash data representing updated portions of firmware of the device 200.

[00104] Attention is next directed to Figure 6, which depicts functions 600, estimations 602 and thresholds 604 stored at the database 210, which may be maintained by the device 200 and/or the controller 202.

[00105] For example, as depicted, the database 210 stores a first set of functions 600-1, estimations 602-1 and thresholds 604-1 determined in a first time period, and additional and/or second sets of functions 600-N, estimations 602-N and thresholds 604-N determined in a second time period later than the first time period. For example, there may be one additional and/or second set of sets of functions 600-N, estimations 602-N and thresholds 604-N (e.g., N=2), or there may be more be more than one additional and/or second set of sets of functions 600-N, estimations 602-N and thresholds 604-N (e.g., N>2). A set of functions 600, estimations 602 and thresholds 604 may represent behavior of the flash memory 204 during a respective time period, which may change over time.

[00106] As has been previously described, the functions 600-1...600-N include, but are not limited to, respective 64 KB erase functions, 32 KB erase functions, 4 KB erase functions and page program functions determined as described above with respect to Figure 4.

[00107] As has been previously described, the estimations 602-1...602-N include, but are not limited to, respective 64 KB erase+program estimations, 32 KB erase+program estimations, a 4 KB erase+program estimations, described above with respect to the method 500.

[00108] As has been previously described, the thresholds 604-1...604-N include, but are not limited to, respective 64 KB erase+program thresholds and 32 KB erase+program thresholds, described above with respect to the method 500.

[00109] Hence, there may be “N” number of sets of functions 600, estimations 602 and thresholds 604, determined at successive time periods. For example, a set of functions 600, estimations 602 and thresholds 604 may be determined periodically, and/or when a given set of sets of functions 600, estimations 602 and thresholds 604 results in more one status check, and/or after a given number of transactions have occurred at the device 200, and/or using any other suitable metric. Indeed, a set of functions 600, estimations 602 and thresholds 604 are understood to be the functions, estimations, and thresholds described above with respect to the method 500. A current set of functions 600, estimations 602 and thresholds 604 may be the set that was most recently determined such as the second set of functions 600-N, estimations 602-N and thresholds 604-N.

[00110] In some examples, the device 200 and/or the controller 202 may determine aging of the flash memory 204 by comparing at least the functions 600 with one another. For example, returning briefly to Figure 4, when lines (e.g., such as the line 404) represented by the functions 600 drift, over time, towards the line 408 which represents cumulative durations (and/or cumulative delay times) for the operations if a respective maximum delay time from the data 218 had been used, the flash memory 204 may be approaching an end-of life cycle.

[00111] Hence, in some examples, the device 200 and/or the controller 202 may determine when a line (e.g., such as the line 404) represented by the functions 600 is within a given distance and/or percentage of the line 408, which represents cumulative durations (and/or cumulative delay times) for the operations if a respective maximum delay time from the data 218 had been used, the device 200 and/or the controller 202 may control a notification device of the device 200, such as a display screen, to provide a notification that the flash memory 204 is to be replaced and/or is approaching end of life. It is understood, however, that such a determination need not be performed graphically; rather slope (e.g., “m”) and intercept (e.g., “b”) components of a function 600 may be compared to respective slope and intercept components of a function representing the line 408, and when the slope (and intercept (e.g.,

“b”) components of the function 600 are within respective threshold distances and/or values from the respective slope and intercept components of the function representing the line 408 (e.g., 5%, 10%, among other possibilities), the device 200 and/or the controller 202 may control a notification device of the device 200, such as a display screen, to provide a notification that the flash memory 204 is to be replaced and/or is approaching end of life.

[00112] Put another way, the method 500 may further comprise the device 200 and/or the controller 202 regenerating the functions 600 over time; and comparing later functions (e.g., functions 600-N) to earlier functions (e.g., functions 600-1) to track aging of the flash memory 204.

[00113] While not depicted, the database 210 may store other information, including, but not limited to, functions and/or erase+program command cycle estimations and/or thresholds for respective given command types that are based on the typical delay times and/or maximum delay times of the data 218. Such functions and/or erase+program command cycle estimations and/or thresholds may also be generated by the device 200 and/or the controller 202 and/or determined by the device 200 and/or the controller 202 by writing data to the flash memory using the typical delay times and/or maximum delay times of the data 218. Such functions and/or erase+program command cycle estimations and/or thresholds may be used as baselines for varying the delay time and/or determining aging of the flash memory 204.

[00114] Attention is next directed to Figure 7 which depicts examples of estimations 700 of 4 KB erase+program durations for different numbers of pages, as well as an estimation 702 of a 32 KB erase+program duration and an estimation 704 of a 34 KB erase+program duration.

[00115] For example, the estimation 702 of the 32 KB erase+program duration may be determined from a 32 KB erase function for a single 32 KB erase command using a number of 1 as an input to the function, and a page program function using a number of 8 page program commands as an input to the function. As depicted, the estimation 702 is 340 ms and represents an estimated duration of one 32 KB erase+program command cycle.

[00116] Similarly, the estimation 704 of the 64 KB erase+program duration may be determined from a 64 KB erase function for a single 64 KB erase command using a number of 1 as an input to the function, and a page program function using a number of 8 page program commands, and a page program function using a number of 16 page program commands as an input to the function. As depicted, the estimation 704 is 590 ms and represents an estimated duration of one 64 KB erase+program command cycle.

[00117] Similarly an estimation 700 of one 4 KB erase+program duration may be determined from a 4 KB erase function for a single 4 KB erase command using a number of 1 as an input to the function, and a page program function using a number of 1 page program command as an input to the function. As depicted, an estimation 700 to write data to one page is 72.5 ms, and represents an estimated duration of one 4 KB erase+program command cycle. As single 4 KB erase+program command cycles may be used serially to write data to respective page, an estimation 700 of two 4 KB erase+program durations is 2x72.5, or 145 ms. Similarly, an estimation 700 of an integer “M” number of 4 KB erase+program durations is Mx72.5. Hence, for example, to write data to 5 pages, a duration of 362.5 ms is estimated (e.g., 5x 72.5), and to write data to 9 pages, a duration of 652.5 ms is estimated (e.g., 9x 72.5).

[00118] Comparing the estimation 702 to the estimations 700, it is apparent that 5 pages and/or 54 KB erase+program command cycles is the smallest number of the 4 KB erase+program command cycles that has a longer duration than a 32 KB erase+program command cycle. Put another way, the estimation 700 of 362.5 ms for 5 pages is the smallest estimation 700 that is above the estimation 702 of 340 ms for a 32 KB erase+program command cycle (e.g., as the next smallest estimation is 290 ms, which is below 340 ms). As such a 32 KB erase+program threshold 706 may be 5 pages and/or 362.5 ms.

[00119] Similarly, comparing the estimation 704 to the estimations 700, it is apparent that 9 pages and/or 94 KB erase+program command cycles is the smallest number of the 4 KB erase+program command cycles that has a longer duration than a 64 KB erase+program command cycle (e.g., as the next smallest estimation is 580 ms, which is below 590 ms). Put another way, the estimation 700 of 652.5 ms for 9 pages is the smallest estimation 700 that is above the estimation 704 of 590 ms for a 64 KB erase+program command cycle. As such a 64 KB erase+program threshold 708 may be 9 pages and/or

652.5 ms

[00120] Such thresholds 706, 708 may be used to selecting erase+program command cycles of different given lengths as described above with respect to the method 500. Furthermore, such thresholds 706, 708 may correspond to the thresholds 604 described with respect to Figure 6.

[00121] Yet further features are within the scope of the present specification as next described with respect to Figure 8 which depicts another example device 800 to minimize delay times for status checks to a flash memory. The device 800 is substantially similar to the device 100 or the device 200, with like components having like numbers, but in a “800” series rather than a “100” series or a “200” series. As such, the device 800 includes a controller 802 and a flash memory 804, which are respectively substantially similar to the controller 202 (and/or the controller 102) and the flash memory 204 (and/or the flash memory 104). While details of the flash memory 804 are not depicted, the flash memory 804 may have a same and/or similar structure as depicted at the flash memory 204 in Figure 2.

[00122] As depicted, the device 800 further comprises a non-transitory computer-readable medium 806 (which may be similar to non-transitory computer-readable medium components of the memory 206) comprising instructions 808 that, when executed by the controller 802 of the device 800, cause the controller 802 to implement functionality as described herein, which may include, but is not limited to, functionality described with respect to the device 100 and/or the device 200.

[00123] In particular, as depicted, the instructions 808 include various modules which are described hereafter.

[00124] In particular, a database maintenance module 810 may be executed by the controller 802 to maintain a database of functions that relate a number of operations, associated with commands of respective given types, to associated cumulative delay times of the operations that result in a single status check, the commands to perform the operations at a flash memory 804. Such functions may more specifically relate a number of operations to associated cumulative durations of the operations that include delay times that result in a single status check. Such functions may include the functions 600 and/or any other suitable functions. Furthermore, the database maintained by controller 802 executing the database maintenance module 810 may be similar to the database 210.

[00125] A duration determination module 812 may be executed by the controller 802 to use the functions of the database (e.g., maintained by the controller 802 executing the database maintenance module 810) to determine durations for erase+program command cycles of different lengths, the durations maintained at the database. Determination of such durations have been described with respect to Figure 5, Figure 6, and Figure 7.

[00126] A threshold determination module 814 may be executed by the controller 802 to use the functions (and/or the durations determined by the controller 802 executing the database maintenance module 810) to determine thresholds for selecting the erase+program command cycles of different lengths, the thresholds maintained at the database.

[00127] Determination of such thresholds have been described with respect to Figure 5, Figure 6, and Figure 7. However, it is understood that the instructions 808 and/or threshold determination module 814, when executed by the controller 802, may be further to: determine a single-page erase+program command cycle duration; and use the single-page erase+program command cycle duration to determine the thresholds for using block erase+program command cycles.

[00128] A command selection module 816 may be executed by the controller 802 to select, using the thresholds and the durations (e.g., determined by the controller 802 executing duration determination module 812 and threshold determination module 814), an erase+program command cycle of a given length that results in a shortest duration for writing given data to the flash memory 804. [00129] Such selection of commands have been described with respect to Figure 5, Figure 6, and Figure 7. However, it is understood that the instructions 808 and/or command selection module 816, when executed by the controller 802, may be further to: when a combination of shorter single-page erase commands, and respective corresponding program commands, for writing the given data to the flash memory 804, has a duration that is greater than a threshold for using a block erase+program command, use the block erase+program command to write the given data to the flash memory 804. [00130] Similarly, it is understood that the instructions 808 and/or command selection module 816, when executed by the controller 802, may be further to: when a combination of shorter single-page erase commands, and respective corresponding program commands, for writing the given data to the flash memory, has a duration that is less than a threshold for using a block erase+program command, use the combination of the shorter single-page erase commands, and respective corresponding program commands to write the given data to the flash memory 804.

[00131] Furthermore, the instructions 808 and/or command selection module 816, when executed by the controller 802, may be further to: make determinations about combinations of block erase+program commands on a basis of adjacent sectors and/or on block-by-block by block basis. An example of such an implementation is described below with respect to Figure 9.

[00132] Furthermore, as depicted, the instructions 808 may further include an aging determination module 818 that, when executed by the controller 802, may be to: regenerate the functions (e.g., as maintained at the database via the controller 802 executing the database maintenance module 810) overtime; and compare later functions to earlier functions to track aging of the flash memory 804.

[00133] Referring to Figure 9, a flowchart of another example method 900 to minimize delay times for status checks to a flash memory is depicted. In order to assist in the explanation of method 900, it will be assumed that the method 900 may be performed at least partially by the device 800, and/or the controller 802 thereof, implementing the method 900 for example by executing the instructions 808, and specifically the command selection module 816. Indeed, the method 900 may be one way in which the device 800 may be configured. Furthermore, the following discussion of method 900 may lead to a further understanding of the device 800, and its various components. Furthermore, it is to be emphasized, that method 900 may not be performed in the exact sequence as shown, and various blocks may be performed in parallel rather than in sequence, or in a different sequence altogether. Furthermore, the method 900 may be performed at the device 100 and/or the device 200.

[00134] Hereafter reference will be made to pages and blocks of the flash memory 804, which are understood to be similar to the pages 216 and blocks 214 of the flash memory 204.

[00135] At a block 902, the device 800 and/or the controller 802 counts, at the flash memory 804, pages within blocks to be updated.

[00136] For example, such a count may occur in conjunction with a determination of which pages to within a given block, ora half-block, to update which may occur by comparing data external to the flash memory 804, that is to be stored to the flash memory 804, with presently data stored at the flash memory 804 (which may include, but is not limited to, hash data of device firmware). When a given page at the flash memory 804 stores data that is the same as corresponding external data, the page at the flash memory 804 isn’t counted as there is no need to again write the data to the flash memory 804. However, when a given page at the flash memory 804 stores data that is different from corresponding external data, the page at the flash memory 804 is counted as the new data is to be written to the flash memory 804.

[00137] Furthermore, such a count is understood to be performed on a block basis and/or a half block basis. Put another way, the goal is to identify blocks, and/or half blocks, to which data may be written concurrently and/or using erase+program command cycles (e.g., which may erase and write data on block and/or half block basis) having a shortest duration.

[00138] At a block 904, the device 800 and/or the controller 802, for a given block, or given half-block, compares a number of pages to be updated with block erase+program threshold and/or half block erase+program threshold (e.g., a 64 KB erase+program threshold and/or 32 KB erase+program threshold, as described above); and, at a block 906, the device 800 and/or the controller 802 selects erase+program command cycle(s) that results in a shortest duration for writing given data to the flash memory 804, similar to as described above with respect to Figure 7.

[00139] Hence, for example, for data to be written to one half of a block (e.g., such as the first 8 pages, and not the other half or the last 8 pages), when a half-block erase+program command cycle has a shorter duration to write the data to the half-block than using a suitable number of page erase+program command cycles, the half-block erase+program command cycle is selected. Similarly, for data to be written to a block, when a block erase+program command cycle has a shorter duration to write the data to the block than using a suitable number of page erase+program command cycles, or two half-block erase+program command cycles, the block erase+program command cycle is selected.

[00140] At a block 908, the device 800 and/or the controller 802 places erase commands and program commands of the selected erase+program command cycle(s) into a queue. As block erase commands erase an entire block, and as half-block erase commands erase a half-block, corresponding program commands include corresponding data to write to all of a block or half block, including new data and current data. Put another way, for a block+program command cycle, all pages of a block are erased, and new data is written to all the pages, regardless of whether the data is new data (e.g., for which pages are counted at the block 902), or current data that does not, in principle, need to be erased and written. Similarly, for a half block+program command cycle, all pages of a half-block are erased, and new data is written to all the pages of the half-block, regardless of whether the data is new data (e.g., for which pages are counted at the block 902), or current data that does not, in principle, need to be erased and written. However, such a process may be faster than writing only the new data to the flash memory 804 using individual page erase commands and page write commands. As such, the device 800 (and/or the device 100 and/or the device 200) operates faster and/or more efficiently than when using individual page erase commands and page write commands to write data to the flash memory 804 (and/or the flash memory 104 and/or the flash memory 204). [00141] At a block 910, the device 200 and/or the controller 202 implements the erase commands and the program commands of the selected erase+program command cycle(s) in the queue, at the flash memory 804. For example, the erase commands and the program commands (which are understood to have delay times that result in one status check) are sent to the flash memory 804, serially, for processing.

[00142] In general, processes described herein may be faster than writing new data to a flash memory than when using individual page erase commands and page write commands, and/or when using multiple status checks. As such, devices described herein may generally operate faster and/or more efficiently than when using individual page erase commands and page write commands to write data to the flash memory and/or when using multiple status checks.

[00143] It should be recognized that features and aspects of the various examples provided above may be combined into further examples that also fall within the scope of the present disclosure.

Claims

1. A device comprising: a flash memory; and a controller to: vary delay times between sending commands to the flash memory and status checks to determine when the flash memory has completed implementing the commands; and when a single status check, following a respective delay time, results in the flash memory indicating that a respective command has been implemented, use the respective delay time in determining further delay times for later commands similar to the respective command.

2. The device of claim 1 , wherein the controller is further to vary the delay times by selecting the delay times, for respective command types, based on: a predetermined typical delay time associated with the flash memory; a predetermined maximum delay time associated with the flash memory; or, a combination of the predetermined typical delay time and the predetermined maximum delay time.

3. The device of claim 1 , wherein the controller is further to: collect indications of the delay times, for respective command types, that result in the flash memory indicating that the respective command types have been implemented after single status checks; and discarding other indications of the delay times that result in the flash memory indicating that the respective command types have been implemented using more than one status check.

4. The device of claim 1 , wherein the controller is further to: collect indications of the delay times for the commands of a given type that result in the flash memory indicating that the commands of the given type have been implemented after single status checks; after a given period of time, or a given number of the commands of the given type have resulted in the single status checks, generate a function, using the indications, that relates a number of operations, associated with commands of the given type, to associated cumulative delay times of the operations; and using the function to determine the further delay times for the later commands of the given type.

5. The device of claim 1 , wherein the commands include: block erase commands; half-block erase commands; single-page erase commands;

4 KB erase commands;

32 KB erase commands;64KB erase commands; page program commands; and write enable commands.

6. A method comprising: generating, at a controller of a device that includes a flash memory, functions that relate a number of operations, associated with commands of respective given types, to associated cumulative delay times of the operations that result in a single status check, the commands to perform the operations at the flash memory; using, at the controller, the functions used to determine durations for erase+program command cycles of different lengths; and selecting, at the controller, an erase+program command cycle of a given length that results in a shortest duration for writing given data to the flash memory.

7. The method of claim 6, wherein generating the functions comprise: using a machine learning algorithm to generate the functions; generating linear regressions of the number of operations and the associated cumulative delay times; or a combination of using the machine learning algorithm and generating the linear regressions.

8. The method of claim 6, wherein using the functions used to determine durations for the erase+program command cycles of different lengths comprises: using the functions to determine thresholds for selecting erase+program command cycles of different given lengths, wherein the thresholds are time based, memory-size based, page number based, or a combination.

9. The method of claim 6, wherein selecting the erase+program command cycle of the given length that results in the shortest duration for writing the given data to the flash memory comprises: when a larger block erase command, and corresponding program commands, has a duration for writing the given data to the flash memory that is less than a respective duration of a combination of shorter single-page erase commands, and respective corresponding program commands, for writing the given data to the flash memory, use the larger block erase command, and the corresponding program commands, to write the given data to the flash memory.

10. The method of claim 6, wherein an erase+program cycle is to store hash data at the flash memory.

11. A non-transitory computer-readable medium comprising instructions executable by a controller to: maintain a database of functions that relate a number of operations, associated with commands of respective given types, to associated cumulative delay times of the operations that result in a single status check, the commands to perform the operations at a flash memory; use the functions used to determine durations for erase+program command cycles of different lengths, the durations maintained at the database; use the functions used to determine thresholds for selecting the erase+program command cycles of different lengths, the thresholds maintained at the database; and select, using the thresholds and the durations, an erase+program command cycle of a given length that results in a shortest duration for writing given data to the flash memory.

12. The non-transitory computer-readable medium of claim 11 , wherein the instructions are further to: regenerate the functions over time; and compare later functions to earlier functions to track aging of the flash memory.

13. The non-transitory computer-readable medium of claim 11 wherein the instructions are further to: determine a single-page erase+program command cycle duration; and use the single-page erase+program command cycle duration to determine the thresholds for using block erase+program command cycles.

14. The non-transitory computer-readable medium of claim 11, wherein the instructions are further to: when a combination of shorter single-page erase commands, and respective corresponding program commands, for writing the given data to the flash memory, has a duration that is greater than a threshold for using a block erase+program command, use the block erase+program command to write the given data to the flash memory.

15. The non-transitory computer-readable medium of claim 11, wherein the instructions are further to: when a combination of shorter single-page erase commands, and respective corresponding program commands, for writing the given data to the flash memory, has a duration that is less than a threshold for using a block erase+program command, use the combination of the shorter single-page erase commands, and respective corresponding program commands to write the given Ċ data to the flash memory.