CN112074904B - Memory start-up voltage management - Google Patents
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- CN112074904B CN112074904B CN201980029054.1A CN201980029054A CN112074904B CN 112074904 B CN112074904 B CN 112074904B CN 201980029054 A CN201980029054 A CN 201980029054A CN 112074904 B CN112074904 B CN 112074904B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/20—Initialising; Data preset; Chip identification
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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- G11C21/00—Digital stores in which the information circulates continuously
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Abstract
A system includes a memory device that stores a set of starting voltage values, wherein the set of starting voltage values each represent a voltage level for initially storing charge when performing an operation on a corresponding one or more memory locations of the memory device; and a processing device operably coupled to the memory device to: determining whether a number of firing voltage values in the set of firing voltage values stored in the memory device reaches a threshold; modifying the set of firing voltage values stored in the memory device to remove one or more firing voltage values from the set in response to determining that the number of firing voltage values in the set reaches the threshold; and adding the new starting voltage value to the set of modified starting voltage values.
Description
Technical Field
The disclosed embodiments relate to memory systems, and in particular, to memory launch voltage management.
Background
Memory systems may employ memory devices to store and access information. The memory device may include a volatile memory device, a non-volatile memory device, or a combination of devices. Non-volatile memory devices may include flash memory employing "NAND" technology or logic gates, "NOR" technology or logic gates, or a combination thereof.
Memory devices, such as flash memory, utilize electrical energy and corresponding threshold levels or processing voltage levels to store and access data. However, the performance or characteristics of flash memory devices change or degrade over time or use. The change in performance or characteristic conflicts with the threshold or process voltage level over time, causing errors and other performance problems.
Drawings
FIG. 1 illustrates an example computing environment including a storage system according to some embodiments of the invention.
FIG. 2 illustrates a block diagram of an example of monitoring capacity in a memory block list, according to some embodiments of the invention.
FIG. 3 is a flow diagram illustrating an example method for managing storage capacity of a starting voltage according to an embodiment of the invention.
Figures 4A and 4B illustrate block diagrams of examples of freeing capacity in a memory block list for a starting voltage value, according to some embodiments of the invention.
FIG. 5 is a block diagram of an example computer system in which embodiments of the present invention may operate.
Detailed Description
Aspects of the present invention relate to managing a start-up voltage of a memory system. An example of a memory system is a storage system, such as a Solid State Drive (SSD). In general, a host system may utilize a memory system that includes one or more memory devices. The memory device may comprise a non-volatile memory device such as, for example, a "NAND" (NAND). The host system may provide write requests to store data at a memory device of the memory system and may provide read requests to retrieve data stored at the memory system. For an initial write operation, the memory device may store charge to the memory cells of a particular memory location for the write operation. The memory device may store a program start voltage based on an initial write operation to the particular memory location (e.g., memory block, word line, or a combination thereof). Conventional memory devices may each utilize a memory block list to track the starting voltage level used to program the corresponding memory block/word line. For subsequent programming events (e.g., write operations) to the particular memory location, the memory system (e.g., SSD) may reference a stored programming start voltage, which may result in a modifiedTime to program ("Tprog") performance. However, the number of program start voltages that some conventional memory systems can store may be limited. The conventional memory block list may have a maximum capacity for tracking a maximum number of starting voltage levels. Once the block list becomes full, subsequent open block flows (e.g., a set/sequence of write/program operations occurring for corresponding blocks, word lines, etc.) may not benefit from tracking the start-up voltage level. Consequently, subsequent open block flows of a conventional memory system may experience a more undesirable TprogAnd (4) performance.
Aspects of the present invention address the above and other shortcomings by dynamically managing a memory block list of a memory device and freeing capacity on the memory block list to track new startup voltage levels. Aspects of the present disclosure describe managing memory block lists, for example, based on tracking recently used open block flows. Aspects of the disclosure describe managing a memory block list, e.g., based on determining whether a memory block is near and/or has reached a maximum capacity, and in response, managing one or more entries in the memory block list to free up capacity.
FIG. 1 is a block diagram of an example computing system 100 including a memory system 102, according to some embodiments of the invention. Memory system 102 may include media, such as memory devices 104A-114N. The memory devices 104A-104N may be volatile memory devices, non-volatile memory devices, or a combination of such devices. In some embodiments, memory system 102 is a storage system. An example of a storage system is a Solid State Drive (SSD). In general, the computing system 100 may include a host system 108 that uses the memory system 102. For example, host system 108 can write data to memory system 102 and read data from memory system 102.
Host system 108 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, or such a computing device that includes memory and a processing device. Host system 108 can include or can be coupled to memory system 102 such that host system 108 can read data from memory system 102 or write data to memory system 102. Host system 108 may be coupled to memory system 102 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components that may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, etc. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, fibre channel, serial attached scsi (sas), and the like. The physical host interface may be used to transfer data between the host system 108 and the memory system 102. When the memory system 102 is coupled with the host system 108 over a PCIe interface, the host system 108 may further utilize an NVM express (NVMe) interface to access the memory devices 104A-104N. The interface may provide an interface for passing control, address, data, and other signals between the memory system 102 and the host system 108.
The memory devices 104A-104N may include different types of non-volatile memory devices and/or any combination of volatile memory devices. Examples of non-volatile memory devices include NAND (NAND) type flash memory. Each of memory devices 104A-104N may include one or more arrays of memory cells, such as Single Level Cells (SLC), multi-level cells (MLC) (e.g., Three Level Cells (TLC) or four level cells (QLC)). In some embodiments, a particular memory device includes multiple types of arrays of memory cells, such as, for example, both SLC memory cells and MLC memory cells. Each of the memory cells may store one or more bits of data (e.g., a block of data) used by the host system 108. Although non-volatile memory devices are described, such as NAND type flash memory, the memory devices 104A-104N may be based on any other type of non-volatile memory or volatile memory. For example, memory devices 104A-104N may be, but are not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Phase Change Memory (PCM), Magneto Random Access Memory (MRAM), "NOR" (NOR) flash memory, Electrically Erasable Programmable Read Only Memory (EEPROM), and cross-point arrays of non-volatile memory cells. A cross-point array of a non-volatile memory may perform bit storage based on the bulk resistance change in conjunction with a stacked cross-grided data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform an in-place write operation in which non-volatile memory cells can be programmed without having been previously erased. Further, the memory cells of the memory devices 104A-104N may be grouped into memory pages or data blocks, which may refer to a unit of memory devices used to store data.
The memory system controller 106 may communicate with the memory devices 104A-104N to perform operations, such as reading data, writing data, or erasing data at the memory devices 104A-104N, and other such operations. Further, the memory system controller 106 may include hardware, such as one or more integrated circuits and/or discrete components, processing devices, buffer memory, software, such as firmware or other instructions, or a combination thereof. In general, the memory system controller 106 may receive commands or operations from the host system 108 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 104A-104N. The memory system controller 106 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, cache operations, and address translation between logical and physical block addresses associated with the memory devices 104A-104N. The memory system controller 106 may further include host interface circuitry to communicate with the host system 108 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory devices 104A-104N and also convert responses associated with the memory devices 104A-104N into information for the host system 108.
The memory system controller 106 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor. The memory system controller 106 may include a processor 120 (processing device) configured to execute instructions stored in a local memory 122. In the illustrated example, the local memory 122 of the memory system controller 106 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory system 102, including handling communications between the memory system 102 and the host system 108. In some embodiments, local memory 122 may include memory registers that store, for example, memory pointers, fetched data, and the like. The local memory 122 may also include Read Only Memory (ROM) for storing microcode. Although the example memory system 102 in FIG. 1 has been illustrated as including the memory system controller 106, in another embodiment of the present disclosure, the memory system may not include a memory system controller, and may instead rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory system).
The media devices 104A-104N may include media controllers 121A-121N for creating data structures including programmed start voltages for the media devices 104A-104N. In some embodiments, the data structure is a list (hereinafter referred to as a "block list" or "memory block list"). The memory block list is described in more detail below in connection with FIG. 2. The memory block list may store a starting voltage that may be used to write/program the corresponding block stream. Each of the block streams may represent a set/sequence of write/program operations that occur for a corresponding block, word line, or combination thereof. In some embodiments, one memory block list may store a starting voltage of one of the memory devices 104A-104N. In some embodiments, one memory block list may store the starting voltages of more than one or all of the memory devices 104A-104N.
The memory system 102 can include a startup voltage management component 113 for tracking and managing a set of startup voltages (e.g., an example of a program startup voltage for a set of bank-wordline combinations). In one embodiment, the memory system controller 106 includes a startup voltage management component 113. For example, the memory system controller 106 may include a processor 120 (processing device) configured to execute instructions stored in a local memory 122 for tracking and managing a set of starting voltages. The starting voltage management component 113 can determine whether the list of memory blocks has reached maximum capacity and/or is near maximum capacity, and can free capacity for storing new starting voltage values, as described in more detail below.
FIG. 2 illustrates a block diagram of an example of monitoring capacity in a memory block list, according to some embodiments of the invention. The memory block list 212 may store a set of firing voltages 252A-252N for the most recently stored memory blocks/word lines. For example, starting from an empty list (e.g., such as at memory system boot-up or after a reset event), one or more of the memory devices 104A-104N may determine a program start voltage (e.g., program start voltage 252A) when the memory location is first written/programmed. When a program start voltage (e.g., program start voltage 252A) is determined, the respective memory device 104 may store it in the memory block list 212. As the memory device 104 performs write/program operations on different memory blocks for the first time, the memory device 104 may similarly determine and store the starting voltages 252A-252N in the memory block list 212.
The memory block list 212 may include slots/registers for storing the firing voltage values 252A-252N. Starting electric motorEach entry of pressure value 252 may include an index identifier 253A-253N. The starting voltage values 252A through 252N may be represented as "B1stV[…]", which includes a starting voltage value" B "for the first memory blocknthV[…]", which includes the starting voltage value of the nth memory block. Each starting voltage value entry in the memory block list 212 may be used to program a corresponding block stream 206A-206N. Each of the block streams 206A-206N may represent a set/sequence of write/program operations occurring with a corresponding block (e.g., blocks 208A-208N), word line, or a combination thereof.
The memory block list 212 may have a maximum capacity (e.g., a maximum storage capacity) for storing the starting voltage. The maximum capacity may correspond to the maximum number of blocks/word lines that can be tracked at one time. For example, the memory block list 212 may have a maximum capacity 'N', e.g., for tracking the starting voltages 252A-252N corresponding to N different memory blocks.
The memory block list 212 may include one or more status indicators (e.g., status 216) that indicate when the memory block list 212 reaches one or more thresholds. In some embodiments, the threshold is set to match the maximum capacity. In some embodiments, the threshold is set to be less than the maximum capacity (e.g., n-1). The threshold may be predefined and/or may be user configurable. In some embodiments, the startup voltage management component 113 detects when the memory block list 212 is near maximum capacity and/or has reached maximum capacity using the status indicator 216, and may modify the memory block list 212 to release capacity in order to store one or more new startup voltages for subsequent corresponding write/program operations in the memory block list 212.
Modifying the memory block list 212 to release capacity and store the starting voltages 252A-252N of the most recently accessed/written/programmed blocks provides simplified memory device starting voltage management of multiple streams in the memory system 102. Thus, the startup voltage management component 113 can help maintain a maximum T in the face of multiple open block flows requiring reduced firmware overheadprogAnd (4) performance. Based on tracking open block flows recently used, the startup voltage management component 113 can track open block flows with a higher likelihood of subsequent accesses using the memory block list 212And (c) to thereby further increase performance gain.
FIG. 3 is a flow diagram illustrating an example method 300 for managing storage capacity of a starting voltage. Method 300 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by the startup voltage management component 113 of fig. 1.
At block 302, the processing device determines whether a number of starting voltage values in a set of starting voltage values stored in the memory device reaches a threshold. In some embodiments, the threshold is set to match the maximum capacity. In some embodiments, the threshold is set to be less than the maximum capacity (e.g., n-1). The threshold may be predefined and/or may be user configurable. The determination of whether the number of starting voltage values in a set of voltage values reaches a threshold may be triggered based on timing, recognition of an event/input condition, and the like. The determination may be triggered autonomously, i.e. without any command or interaction from other external components/devices. In some embodiments, the determination is triggered by a process, set of instructions, hardware, or circuitry configured to implement time-based event-driven pacing (e.g., for a monitor pacing timer mechanism). For example, the time-based event-driven pacing may be based on a set duration/frequency for checking the occupancy/availability status of the memory block list 212 of fig. 2.
In some embodiments, the determination is triggered by a process, a set of instructions, hardware or circuitry, or the like, configured to implement event-based pacing. For example, the processing device may check the occupancy/availability status of memory block list 212 just prior to the first program within the newly opened block. In other words, the processing device may check the occupancy/availability status whenever a memory block becomes open (e.g., after an erase operation, after garbage collection, etc.). Also, for example, the processing device may check the busy/availability status of memory block list 212 whenever the processing device sends a write/program command to memory devices 104A-104N.
The processing device may make the determination by accessing/reading the memory block list 212. For example, the processing device may read the memory block list 212 to determine whether any of the slots/registers in the memory block list 212 are empty, such as including a predetermined value or not including any value.
In some embodiments, the processing device may read the memory block list 212 using a check status command. The check status command may include pre-stored or pre-configured commands/instructions for operating/accessing the memory block list 212. For example, the check status command may correspond to an existing Get Feature 0xDC function included in an Automatic Dynamic Word Line Start Voltage (ADWLSV) mechanism implemented in the memory devices 104A-104N. The ADWLSV mechanism and/or its function may determine and store the starting voltages 252A-252N autonomously (e.g., without any activate and maintain commands/instructions from outside the memory devices 104A-104N).
When the number of slots/registers in the memory block list 212 that store instances of the program launch voltages 252A-N reaches a threshold value, the processing device may update one or more status indicators 216. For example, there may be one status indicator set to a threshold of the maximum capacity (e.g., n) of the memory block list 212. When all slots/registers in the memory block list 212 that store instances of the program start voltages 252A-N reach a threshold (e.g., a maximum capacity threshold), the processing device may set the corresponding status indicator to active or true. In another example, there may be a threshold set to less than the maximum capacity (e.g., n-1) of memory block list 212. When the number of slots/registers in the memory block list 212 that store instances of the program start voltages 252A-N reaches a threshold (e.g., less than a maximum capacity threshold), the processing device may set the respective status indicator to active or true. In some embodiments, there is a threshold set to the maximum capacity of the memory block list 212 and an additional threshold set to less than the maximum capacity (e.g., n-1) of the memory block list 212. Referring to FIG. 3, at block 304, if a determination is made that the number of starting voltage values in the set of starting voltage values does not reach the threshold, then the processing device, when triggered at block 302, makes another determination, for example, based on a time-based pace and/or an event-based pace. Thus, the memory devices 104A-104N may continue to operate, including determining the program start voltages 252A-252N of the newly opened or newly calibrated memory blocks/word lines and storing the newly determined program start voltages 252A-252N in the memory block list 212.
If, at block 304, a determination is made that the number of starting voltage values in the set of starting voltage values reaches a threshold, then the processing device modifies, at block 306, the set of starting voltage values stored in the memory device. The processing device may modify a set of starting voltage values stored in a memory block list 212 of the memory device. The processing device may modify the set of starting voltage values, for example, by removing one or more of the starting voltage values 252A-252N stored in the memory block list 212.
Figures 4A-4B illustrate block diagrams of examples of freeing capacity in a memory block list for a starting voltage value, according to some embodiments of the invention. For example, the memory system controller 106 may command the memory device 104A to perform a write/program operation on the (n +1) th memory block 410 after the memory block list 412 has reached the maximum capacity of n different starting voltages. In such cases, the starting voltage management component 113 can manage the memory block list 312 to free up capacity in the memory block list 212 in order to add a new starting voltage corresponding to the write/program operation on the (n +1) th memory block. The starting voltage management component 113 can, for example, erase one or more of the previously stored starting voltages (e.g., one or more of the n-1 starting voltages) in the memory block list 412 in order to store the starting voltage of the (n +1) th memory block 410.
In some embodiments, such as illustrated in FIG. 4A, the starting voltage management component 113 may clear or reset the memory block list 412 based on removing a previously stored starting voltage. The startup voltage management component 113 can reset the memory block list 412 based on the state 416 with or without receiving additional write/program requests for new blocks. Once the memory block list 412 is cleared, the memory device 104 can determine a program start voltage for an additional (e.g., (n +1) th) block associated with the new/incoming write/program request, and the start voltage management component 113 can store the program start voltage 452A for the additional (e.g., (n +1) th) block in a register corresponding to the entry identifier 452A.
In some embodiments, such as illustrated in FIG. 4B, the boot voltage management component 113 may update the memory block list 412 based on removing the oldest instance in the boot voltage. For example, the memory block list 412 may be implemented using a first-in-first-out (FIFO) memory structure (e.g., a buffer). As illustrated in FIG. 4B, the starting voltage management component 113 can discard or erase the first/oldest instance of the starting voltage previously listed in register 1 (e.g., B in FIG. 2) based on receiving a write/program request involving the (n +1) th block1st V[…]252A) In that respect In some embodiments, the starting voltage management component 113 can shift the remaining starting voltage such that the oldest value (e.g., B2nd V[…]) Is always stored in the designated register (e.g., register 1) corresponding to the oldest entry identifier 453A. The latest start voltage 460 of, for example, the (N +1) th block 410 may also be stored at another designated register (e.g., register N453N). In some embodiments, the launch voltage management component 113 can shift according to write/program access, such as by having a launch voltage for the most recently accessed memory location at the top/bottom of the list and having other launch voltages sorted accordingly.
In some embodiments, the memory block list 312 is implemented using a circular buffer, and the starting voltage management component 113 tracks the oldest/newest entry in the list using the oldest entry identifier 453A (e.g., a pointer or index). Based on the oldest entry identifier 453A, the startup voltage management component 113 can write/program the oldest entry with the newest startup voltage, and then shift the oldest entry tag 453A accordingly.
In some embodiments, the startup voltage management component 113 may include timers that each track a duration of time since a last write/program access to a corresponding memory location (e.g., a last activity of a corresponding open block flow). The startup voltage management component 113 may use the timer value to determine the oldest entry.
The starting voltage management component 113 may remove one or more of the starting voltage values, as discussed above. For example, in some embodiments, the startup voltage management component 113 may update the memory block list 412 based on clearing the memory block list 412. For example, the startup voltage management component 113 can clear/reset the memory block list 412 and remove one or more (e.g., all) of the values stored therein. The startup voltage management component 113 may clear the memory block list 412 using a reset list command (e.g., existing Set Feature 0xDC for the ADWLSV mechanism). In some embodiments, the boot voltage management component 113 can update the memory block list 412 based on the oldest of the boot voltages in the remove/replace memory block list 412. For example, the starting voltage management component 113 can trigger an update when a new instance of the starting voltage (e.g., the (n +1) th starting voltage) is determined.
Referring to FIG. 3, at block 308, the processing device adds the new starting voltage value to a set of modified starting voltage values in the memory device. The processing device may store a new instance of the starting voltage in the space/resource previously occupied by the oldest entry. For example, the processing device may store a new starting voltage according to the oldest entry tag, and then update the oldest entry tag.
In some embodiments, the processing device causes a dummy operation (e.g., a dummy read operation) to be performed. The dummy operation may include an operation that is autonomously triggered/initiated by the memory device without any host command/interaction. The dummy operation may be used to complete a process/sequence, such as to complete an update process of the memory block list 412.
The processing device may execute and/or trigger the memory device 104 to perform a dummy read that includes one or more autonomously triggered/initiated read operations. In some embodiments, a dummy read may be performed on the memory device 104 according to the ADWLSV mechanism. In some embodiments, the memory cells to be read for the dummy read operation are randomly selected. In some embodiments, a predetermined set of memory cells are read for a dummy read operation. In some embodiments, the dummy read may include a read from one of the open block streams (e.g., the stream corresponding to the most recent program start voltage). The processing device and/or memory device 104 may ignore or discard the results of the dummy read.
Fig. 5 illustrates an example machine of a computer system 500 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. For example, the computer system 500 may correspond to a host system (e.g., the host system 108 of fig. 1) that includes or utilizes a storage system (e.g., the memory system 102 of fig. 1) or may be used to perform the operations of a controller (e.g., execute an operating system to perform operations corresponding to the startup voltage management component 113 of fig. 1). In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.
The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.
The data storage 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software 526 embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and/or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, data storage 518, and/or main memory 504 may correspond to the memory system 102 of fig. 1.
In one implementation, the instructions 526 include instructions to implement functionality corresponding to a programming component (e.g., the starting voltage management component 113 of FIG. 1). While the machine-readable storage medium 524 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.
Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, aspects of the present invention may be directed to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.
The present invention also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein.
The present invention may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and so forth.
In the foregoing specification, embodiments have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the invention as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
The term "processing" as used includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, computing results, executing instructions, assembling, transferring, and/or manipulating data structures. The term data structure encompasses information arranged as bits, words or code words, blocks, files, input data, system-generated data (e.g., computed or generated data), and program data. Further, the term "dynamic" is used to describe a process, function, action, or implementation that occurs during operation, use, or deployment of a corresponding device, system, or embodiment and after or while running manufacturer or third party firmware. The dynamically occurring processes, functions, acts or implementations may occur after design, manufacture, and initial test, setup or configuration.
Claims (23)
1. A memory system, comprising:
a memory device that stores a set of firing voltage values, wherein the set of firing voltage values each represent a voltage level for initially storing charge when an operation is performed on a corresponding one or more memory locations of the memory device; and
a processing device operably coupled to the memory device to:
determining whether a number of firing voltage values in the set of firing voltage values stored in the memory device reaches a threshold;
modifying the set of firing voltage values stored in the memory device to remove one or more firing voltage values from the set in response to determining that the number of firing voltage values in the set reaches the threshold, wherein the one or more firing voltage values are removed based on:
tracking an oldest entry within a list of memory blocks, wherein the oldest entry represents one of the starting voltage values corresponding to one of the memory locations that has the longest delay and/or is accessed first since a last access or charge operation, and
deleting the oldest entry; and
the new starting voltage value is added to the set of modified starting voltage values.
2. The memory system of claim 1, wherein determining whether a number of firing voltage values in the set of firing voltage values reaches a threshold value is triggered according to a predetermined pace.
3. The memory system of claim 1, wherein determining whether a number of firing voltage values in the set of firing voltage values reaches a threshold is triggered when a memory block becomes open and before a first operation is performed on an open memory block.
4. The memory system of claim 1, wherein the processing device is further configured to perform a dummy operation after modifying the set of cranking voltage values.
5. The memory system of claim 1, wherein the processing device is configured to:
determining whether the number of fire voltage values in the set of fire voltage values reaches a threshold using an automatic dynamic word line fire voltage, ADWLSV, of the memory device; and
removing the one or more of the cranking voltage values using a set-up feature function of ADWLSV.
6. The memory system of claim 1, wherein the processing device is configured to remove the one or more of the cranking voltage values based on resetting a list of memory blocks to clear the set of stored cranking voltage values.
7. The memory system of claim 1, wherein:
the set of starting voltage values is stored using a circular buffer; and is
The processing device is configured to track the oldest entry among the starting voltage values that is stored first.
8. The memory system of claim 1, wherein:
the memory device comprises a NAND die; and is
The set of starting voltage values is stored in the NAND die.
9. The memory system of claim 1, wherein the starting voltage value corresponds to a plurality of block streams, wherein each block stream is a set of data and/or charge operations scheduled for a corresponding block of the memory device, a word line of the memory device, or a combination thereof.
10. The memory system of claim 1, wherein the processing device is configured to perform operations based on iteratively storing charge in a calibration memory cell according to an Incremental Step Pulse Programming (ISPP) mechanism, wherein:
a first charge iteration of the ISPP mechanism charges according to one of the starting voltage values that corresponds to a calibration memory cell, and
the starting voltage values are each used to reduce the number of iterations used to complete the corresponding operation.
11. A method for a memory system, comprising:
determining whether a number of firing voltage values in a set of firing voltage values stored in a memory device reaches a threshold, wherein the set of firing voltage values each represent a voltage level for initially storing charge when performing an operation on a corresponding one or more memory locations of the memory device;
modifying the set of firing voltage values stored in the memory device to remove one or more firing voltage values from the set in response to determining that the number of firing voltage values in the set reaches the threshold, wherein the one or more firing voltage values are removed based on:
tracking an oldest entry within a list of memory blocks, wherein the oldest entry represents one of the starting voltage values corresponding to one of the memory locations that has the longest delay and/or is accessed first since a last access or charge operation, and
deleting the oldest entry; and
the new starting voltage value is added to the set of modified starting voltage values.
12. The method of claim 11, wherein determining whether a number of starting voltage values in the set of starting voltage values reaches a threshold value is triggered according to a predetermined pace.
13. The method of claim 11, wherein determining whether a number of firing voltage values in the set of firing voltage values reaches a threshold is triggered when a memory block becomes open and before a first operation is performed on an open memory block.
14. The method of claim 11, further comprising performing a dummy operation after modifying the set of cranking voltage values.
15. The method of claim 11, wherein removing the one or more of the starting voltage values is based on resetting a list of memory blocks to clear the set of stored starting voltage values.
16. The method of claim 11, wherein:
the set of starting voltage values is stored using a circular buffer; and is
The method further includes tracking the oldest entry among the starting voltage values that is stored first.
17. The method of claim 11, wherein the starting voltage value corresponds to a plurality of block streams, wherein each block stream is a set of data and/or charge operations scheduled for a corresponding block of the memory device, a word line of the memory device, or a combination thereof.
18. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
determining whether a number of firing voltage values in a set of firing voltage values stored in a memory device reaches a threshold, wherein the set of firing voltage values each represent a voltage level for initially storing charge when performing an operation on a corresponding one or more memory locations of the memory device;
modifying the set of firing voltage values stored in the memory device to remove one or more firing voltage values from the set in response to determining that the number of firing voltage values in the set reaches the threshold, wherein the one or more firing voltage values are removed based on:
tracking an oldest entry within a list of memory blocks, wherein the oldest entry represents one of the starting voltage values corresponding to one of the memory locations that has the longest delay and/or is accessed first since a last access or charge operation, and
deleting the oldest entry; and
the new starting voltage value is added to the set of modified starting voltage values.
19. The non-transitory computer-readable storage medium of claim 18, wherein determining whether a number of starting voltage values in the set of starting voltage values reaches a threshold is triggered according to a predetermined pace.
20. The non-transitory computer-readable storage medium of claim 18, wherein determining whether a number of starting voltage values in the set of starting voltage values reaches a threshold is triggered when a memory block becomes open and before a first operation is performed on an open memory block.
21. The non-transitory computer-readable storage medium of claim 18, wherein the processing device further performs a dummy operation after modifying the set of cranking voltage values.
22. The non-transitory computer-readable storage medium of claim 18, wherein removing the one or more of the starting voltage values is based on resetting a list of memory blocks to clear the set of stored starting voltage values.
23. The non-transitory computer-readable storage medium of claim 18, wherein:
the set of starting voltage values is stored using a circular buffer; and is
The processing means further tracks the oldest stored entry among the starting voltage values that is first stored.
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| PCT/US2019/025255 WO2019212668A1 (en) | 2018-04-30 | 2019-04-01 | Memory start voltage management |
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| US10878910B2 (en) | 2020-12-29 |
| US20200005870A1 (en) | 2020-01-02 |
| US20190333582A1 (en) | 2019-10-31 |
| US10482965B1 (en) | 2019-11-19 |
| CN112074904A (en) | 2020-12-11 |
| WO2019212668A1 (en) | 2019-11-07 |
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