JP5654480B2 - 均一な読み出し待ち時間のための冗長なデータ記憶 - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7205—Cleaning, compaction, garbage collection, erase control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
Description
半導体メモリは、データ記憶のために多くのコンピュータ及び電子デバイスにより使用されるデジタル記憶装置の一種である。ソリッドステート(半導体)回路のパッケージングは概して、磁気ディスクドライブよりも大きい耐久性かつ低い消費電力を半導体メモリに与える。半導体メモリデバイスの記憶容量の増加および半導体メモリの比較的安価なコストの増進になされてきた継続的な歩みと結びつけられたこれら特徴は、広範囲の用途に半導体メモリを使用することに寄与した。例えば、幾つかの用途において、不揮発性半導体メモリは、磁気ハードディスクに取って代わるために、又はプロセッサが電力供給されていない際に、それらの内容を保持するプロセッサのメモリ空間の領域に使用され得る。
上述したように、以下に限定されないが、フラッシュメモリ及び他の不揮発性半導体メモリを含むデジタル記憶装置の幾つかのタイプにおいて、データをメモリに書き込むために必要な時間量は、データをメモリから読み出すために必要な時間量よりも大幅に長い可能性がある。更に、消去操作は、書き込み操作または読み出し操作に比べて、完了するためのより長い時間量を必要とするかもしれない。
さて、図1Aを参照すると、例示的なメモリ装置(100)が示される。説明のために、本明細書のシステム及び方法は、フラッシュメモリに関して主として説明される。しかしながら、理解されるように、本明細書のシステム及び方法は、任意のタイプのデジタル記憶装置で利用されることができ且つ利用されることが意図されており、この場合、少なくとも1つの書き込み操作または消去操作は、読み出し操作に比べて完了するためにかなり長い時間量を必要とする。本システム及び方法が適用され得るデジタル記憶装置の他のタイプの例は、以下に限定されないが、相変化メモリ(即ち、PRAM)、紫外線消去型メモリ、電気的消去可能ROM(EEPROM)、及び他のプログラム可能不揮発性半導体メモリタイプを含む。
さて、図9Aを参照すると、メモリバンクのアレイにおいて均一な読み出し待ち時間を維持する例示的な方法(900)の流れ図が示される。例えば、方法(900)は、図8に関連して上述されたようなメモリシステム(800、図8)において、管理モジュール(805)の制御下で行われることができ、この場合、データの少なくとも1つの主記憶場所は、書き込み操作又は消去操作を実行するために、読み出し操作よりも多くの時間を必要とする。
Claims (9)
- メモリ装置であって、
複数のメモリバンクを含み、前記メモリバンクに対する書き込み操作または消去操作が、前記バンクに対する読み出し操作よりもかなり遅く、
前記メモリ装置は、前記バンクにおける主記憶場所が書き込み操作および消去操作の少なくとも1つを受けている際にデータの問い合わせに応じて前記主記憶場所に格納されたデータの代わりに冗長な記憶領域に格納されたデータを読み出すように構成され、前記メモリ装置が、前記複数のメモリバンクに格納されたデータに対して実質的に均一な読み出し待ち時間を含み、
前記問い合わせで要求された前記データが、前記複数のメモリバンクのうちの複数の全体にわたって分散され、
前記冗長な記憶領域に格納された前記データがパリティデータを含み、前記要求されたデータが、前記パリティデータ、及び前記複数のメモリバンクのうちの前記複数の全体にわたって分散されたデータの部分から導出される、メモリ装置。 - 前記メモリバンクがフラッシュメモリからなる、請求項1に記載のメモリ装置。
- 前記実質的に均一な読み出し待ち時間が、前記メモリバンクの前記主記憶場所の書き込み待ち時間および消去待ち時間の少なくとも1つよりかなり小さい、請求項1又は2に記載のメモリ装置。
- 前記パリティデータ、及び前記複数のメモリバンクのうちの前記複数の全体にわたって分散されたデータの部分を用いて前記主記憶場所に格納された前記データに対応するデータを生成するように構成された再構成モジュールと、
前記主記憶場所に格納された前記データの代わりに前記再構成モジュールにより生成された前記データを使用するように構成された読み出しマルチプレクサとを更に含む、請求項1〜3の何れかに記載のメモリ装置。 - 複数のメモリバンクからなるアレイにおいて実質的に均一な読み出し待ち時間を維持する方法であって、
データの問い合わせに応じて、前記メモリバンクの主記憶場所が書き込み操作および消去操作の少なくとも1つを現在受けているか否かを判定し、
前記主記憶場所が書き込み操作および消去操作の少なくとも1つを現在受けている場合に、前記主記憶場所に格納されたデータの代わりに冗長な記憶領域に格納されたデータを読み出すことを含み、
前記問い合わせされたデータが、前記複数のメモリバンクからなる前記アレイにおける複数のメモリバンクの個々のメモリバンク全体にわたって分散され、前記冗長な記憶領域に格納された前記データがパリティデータを含み、
前記方法が、前記主記憶場所に格納された前記データに対応するデータを、分散されたデータの部分および前記パリティデータから再構成することを更に含む、方法(900)。 - 前記主記憶場所に格納された前記データの代わりに前記再構成されたデータを使用することにより、前記問い合わせされたデータを導出し、
前記問い合わせされたデータを外部読み出しプロセスに提供することを更に含む、請求項5に記載の方法。 - 前記問い合わせされたデータが一時的な書き込みバッファに格納されているという判定に応じて、前記問い合わせされたデータを前記一時的な書き込みバッファから直接的に読み出すことを更に含む、請求項5又は6に記載の方法。
- 複数のメモリバンクであって、前記メモリバンクに対する書き込み操作または消去操作が、前記メモリバンクに対する読み出し操作よりもかなり遅い、複数のメモリバンクと、
前記メモリバンクの主記憶場所が書き込み操作および消去操作の少なくとも1つを受けているという判定に応じて、前記メモリバンクの前記主記憶場所に格納されたデータを、前記複数のメモリバンクの全体にわたって分散された断片化データ、及び冗長な記憶領域に格納されたパリティデータから再構成するように構成された再構成モジュールと、
前記主記憶場所に格納された前記データの代わりに前記再構成されたデータを使用し、前記再構成されたデータ及び前記断片化データから導出される要求されたデータを提供するように構成された読み出しマルチプレクサとを含む、データ記憶システム。 - 外部プロセスから同期して書き込みデータを受け取り、前記書き込みデータを格納すると同時に、互い違いの書き込みプロセスが前記書き込みデータを前記複数のメモリバンクに書き込むように構成された書き込みバッファを更に含む、請求項8に記載のデータ記憶システム。
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PCT/US2008/087632 WO2010071655A1 (en) | 2008-12-19 | 2008-12-19 | Redundant data storage for uniform read latency |
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EP (1) | EP2359248A4 (ja) |
JP (1) | JP5654480B2 (ja) |
KR (1) | KR101638764B1 (ja) |
CN (1) | CN102257482B (ja) |
WO (1) | WO2010071655A1 (ja) |
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EP2359248A1 (en) | 2011-08-24 |
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