DE112023004212T5 - Leiterplatte und Verfahren zum Herstellen einer Leiterplatte - Google Patents

Leiterplatte und Verfahren zum Herstellen einer Leiterplatte

Info

Publication number
DE112023004212T5
DE112023004212T5 DE112023004212.8T DE112023004212T DE112023004212T5 DE 112023004212 T5 DE112023004212 T5 DE 112023004212T5 DE 112023004212 T DE112023004212 T DE 112023004212T DE 112023004212 T5 DE112023004212 T5 DE 112023004212T5
Authority
DE
Germany
Prior art keywords
layer
fluororesin
circuit board
printed circuit
inorganic filler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112023004212.8T
Other languages
German (de)
English (en)
Inventor
Shingo Kaimori
Satoshi KIYA
Hiroshi Ueda
Motohiko SUGIURA
Eiko Imazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Sumitomo Electric Printed Circuits Inc
Original Assignee
Sumitomo Electric Industries Ltd
Sumitomo Electric Printed Circuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd, Sumitomo Electric Printed Circuits Inc filed Critical Sumitomo Electric Industries Ltd
Publication of DE112023004212T5 publication Critical patent/DE112023004212T5/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4655Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00Layered products comprising a layer of metal
    • B32B15/04Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00Layered products comprising a layer of synthetic resin
    • B32B27/30Layered products comprising a layer of synthetic resin comprising vinyl (co)polymers; comprising acrylic (co)polymers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/015Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0195Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/0959Plated through-holes or plated blind vias filled with insulating material

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Laminated Bodies (AREA)
DE112023004212.8T 2022-10-07 2023-09-04 Leiterplatte und Verfahren zum Herstellen einer Leiterplatte Pending DE112023004212T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2022-162209 2022-10-07
JP2022162209 2022-10-07
PCT/JP2023/032203 WO2024075456A1 (ja) 2022-10-07 2023-09-04 回路基板および回路基板の製造方法

Publications (1)

Publication Number Publication Date
DE112023004212T5 true DE112023004212T5 (de) 2025-08-07

Family

ID=90607792

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112023004212.8T Pending DE112023004212T5 (de) 2022-10-07 2023-09-04 Leiterplatte und Verfahren zum Herstellen einer Leiterplatte

Country Status (4)

Country Link
JP (1) JPWO2024075456A1 (https=)
CN (1) CN119999341A (https=)
DE (1) DE112023004212T5 (https=)
WO (1) WO2024075456A1 (https=)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2678940B1 (fr) * 1991-05-24 1996-10-18 Rogers Corp Film composite charge de particules et procede pour sa fabrication.
JP2690032B2 (ja) * 1991-10-03 1997-12-10 ダイキン工業株式会社 フッ素樹脂積層体およびその製造法
JP2002001886A (ja) * 2000-06-09 2002-01-08 Three M Innovative Properties Co 被接着可能フッ素系材料シート、接着性フッ素系材料シート、フッ素系材料シートの接着方法および接着構造
JP4938199B2 (ja) * 2000-06-14 2012-05-23 出光興産株式会社 ポリオレフィン系ホットメルト接着剤用樹脂
JP7608450B2 (ja) * 2020-05-18 2025-01-06 住友電気工業株式会社 誘電体シートの製造方法、高周波プリント配線板用基板の製造方法、誘電体シート、及び高周波プリント配線板用基板
JP7514157B2 (ja) * 2020-10-12 2024-07-10 日本メクトロン株式会社 スルーホール形成方法およびフレキシブルプリント配線板用基板
JP6981522B1 (ja) * 2020-12-15 2021-12-15 東洋インキScホールディングス株式会社 熱硬化性樹脂組成物、およびその利用

Also Published As

Publication number Publication date
JPWO2024075456A1 (https=) 2024-04-11
WO2024075456A1 (ja) 2024-04-11
CN119999341A (zh) 2025-05-13

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