DE112008002924B4 - Struktur und Herstellung einer speziell für analoge Anwendungen geeigneten Halbleiterarchitektur mit Feldeffekttransistoren - Google Patents

Struktur und Herstellung einer speziell für analoge Anwendungen geeigneten Halbleiterarchitektur mit Feldeffekttransistoren Download PDF

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DE112008002924B4
DE112008002924B4 DE112008002924.5T DE112008002924T DE112008002924B4 DE 112008002924 B4 DE112008002924 B4 DE 112008002924B4 DE 112008002924 T DE112008002924 T DE 112008002924T DE 112008002924 B4 DE112008002924 B4 DE 112008002924B4
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DE112008002924T5 (de
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Constantin Bulucea
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Nat Semiconductor Corp N D Ges D Staates Delaware
National Semiconductor Corp
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Nat Semiconductor Corp N D Ges D Staates Delaware
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/314—Channel regions of field-effect devices of FETs of IGFETs having vertical doping variations 
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/225—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of a molecular ion, e.g. decaborane

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
DE112008002924.5T 2007-10-31 2008-10-02 Struktur und Herstellung einer speziell für analoge Anwendungen geeigneten Halbleiterarchitektur mit Feldeffekttransistoren Active DE112008002924B4 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/981,355 US7838369B2 (en) 2005-08-29 2007-10-31 Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
US11/981,481 2007-10-31
US11/981,355 2007-10-31
US11/981,481 US7642574B2 (en) 2005-08-29 2007-10-31 Semiconductor architecture having field-effect transistors especially suitable for analog applications
PCT/US2008/011463 WO2009058187A1 (en) 2007-10-31 2008-10-02 Structure and fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications.

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DE112008002924T5 DE112008002924T5 (de) 2010-12-02
DE112008002924B4 true DE112008002924B4 (de) 2019-03-28

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JP (1) JP2011519469A (https=)
KR (1) KR20100084642A (https=)
CN (1) CN101971347A (https=)
DE (1) DE112008002924B4 (https=)
TW (1) TWI426564B (https=)
WO (1) WO2009058187A1 (https=)

Families Citing this family (8)

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Publication number Priority date Publication date Assignee Title
US8084827B2 (en) * 2009-03-27 2011-12-27 National Semiconductor Corporation Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses
JP5423269B2 (ja) 2009-09-15 2014-02-19 富士通セミコンダクター株式会社 半導体装置とその製造方法
JP5560812B2 (ja) * 2010-03-23 2014-07-30 富士通セミコンダクター株式会社 半導体装置及びその製造方法
KR102180554B1 (ko) 2013-12-04 2020-11-19 삼성디스플레이 주식회사 박막 트랜지스터 및 이의 제조 방법
US10424581B2 (en) * 2016-04-18 2019-09-24 Samsung Electronics Co., Ltd. Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating
US11251095B2 (en) 2016-06-13 2022-02-15 Globalfoundries Singapore Pte. Ltd. High gain transistor for analog applications
US11288430B2 (en) * 2017-11-27 2022-03-29 Globalfoundries U.S. Inc. Producing models for dynamically depleted transistors using systems having simulation circuits
CN108615675B (zh) * 2018-05-04 2020-12-11 长江存储科技有限责任公司 衬底掺杂结构及其形成方法

Citations (4)

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US6078082A (en) 1995-04-12 2000-06-20 National Semiconductor Corporation Field-effect transistor having multi-part channel
US6127700A (en) 1995-09-12 2000-10-03 National Semiconductor Corporation Field-effect transistor having local threshold-adjust doping
US6548842B1 (en) 2000-03-31 2003-04-15 National Semiconductor Corporation Field-effect transistor for alleviating short-channel effects
US7145191B1 (en) 2000-03-31 2006-12-05 National Semiconductor Corporation P-channel field-effect transistor with reduced junction capacitance

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JP3529549B2 (ja) * 1996-05-23 2004-05-24 東芝マイクロエレクトロニクス株式会社 半導体装置の製造方法
US6548642B1 (en) 1997-07-21 2003-04-15 Ohio University Synthetic genes for plant gums
US6566204B1 (en) * 2000-03-31 2003-05-20 National Semiconductor Corporation Use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors
KR100580796B1 (ko) * 2003-12-10 2006-05-17 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
US7176530B1 (en) * 2004-03-17 2007-02-13 National Semiconductor Corporation Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor

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US6078082A (en) 1995-04-12 2000-06-20 National Semiconductor Corporation Field-effect transistor having multi-part channel
US6127700A (en) 1995-09-12 2000-10-03 National Semiconductor Corporation Field-effect transistor having local threshold-adjust doping
US6548842B1 (en) 2000-03-31 2003-04-15 National Semiconductor Corporation Field-effect transistor for alleviating short-channel effects
US7145191B1 (en) 2000-03-31 2006-12-05 National Semiconductor Corporation P-channel field-effect transistor with reduced junction capacitance

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Title
Buti et al., „Asymmetrical Halo Source GOLD drain (HS-GOLD) Deep Sub-half Micron n-MOSFET Design for Reliability and Performance", IEDM Tech. Dig., 3-6 Dec. 1989, Seiten 26.2.1-26.2.4
Chai et al., „A Cost-Effective 0.25 µm Leff BiCMOS Technology Featuring Graded-Channel CMOS (GSMOS) and a Quasi-Self-Aligned (QSA) NPN for RF Wireless Applications", Procs. 2000 Bipolar/BiCMOS Circs. and Tech. Meeting, 24.-26. Sep. 2000, Seiten 110-113
Cheng et al., „Channel Engineering for High Speed Sub-1.0 V Power Supply Deep Submicron CMOS", 1999 Symp. VLSI Tech., Dig. Tech. Paps., 14.-16. Juni 1999, Seiten 69 and 70
Deshpande et al., „Channel Engineering for Analog Device Design in Deep Submicron CMOS Technology for System on Chip Applications", IEEE Trans. Elec. Devs., Sep. 2002, Seiten 1558-1565
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Matsuki et al., „Laterally-Doped Channel (LDC) Structure for Sub-Quarter Micron MOSFETs", 1991 Symp. VLSI Tech., Dig. Tech. Paps., 28.-30. Mai 1991, Seiten. 113 and 114
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Also Published As

Publication number Publication date
DE112008002924T5 (de) 2010-12-02
TWI426564B (zh) 2014-02-11
WO2009058187A1 (en) 2009-05-07
CN101971347A (zh) 2011-02-09
KR20100084642A (ko) 2010-07-27
TW200924075A (en) 2009-06-01
JP2011519469A (ja) 2011-07-07

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