DE10346581B4 - Verfahren zum Herstellen einer Halbleitervorrichtung - Google Patents

Verfahren zum Herstellen einer Halbleitervorrichtung Download PDF

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Publication number
DE10346581B4
DE10346581B4 DE10346581A DE10346581A DE10346581B4 DE 10346581 B4 DE10346581 B4 DE 10346581B4 DE 10346581 A DE10346581 A DE 10346581A DE 10346581 A DE10346581 A DE 10346581A DE 10346581 B4 DE10346581 B4 DE 10346581B4
Authority
DE
Germany
Prior art keywords
substrate
electrodes
semiconductor device
forming
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10346581A
Other languages
German (de)
English (en)
Other versions
DE10346581A1 (de
Inventor
Yoshihiko Nemoto
Tomonori Fujii
Masahiro Sunohara
Tomotoshi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Taiyo Yuden Co Ltd
Renesas Electronics Corp
Original Assignee
Renesas Technology Corp
Shinko Electric Industries Co Ltd
Sharp Corp
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Shinko Electric Industries Co Ltd, Sharp Corp, Taiyo Yuden Co Ltd filed Critical Renesas Technology Corp
Publication of DE10346581A1 publication Critical patent/DE10346581A1/de
Application granted granted Critical
Publication of DE10346581B4 publication Critical patent/DE10346581B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07234—Using a reflow oven
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/255—Materials of outermost layers of multilayered bumps, e.g. material of a coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE10346581A 2003-01-14 2003-10-07 Verfahren zum Herstellen einer Halbleitervorrichtung Expired - Fee Related DE10346581B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003005766A JP4213478B2 (ja) 2003-01-14 2003-01-14 半導体装置の製造方法
JP2003/005766 2003-01-14

Publications (2)

Publication Number Publication Date
DE10346581A1 DE10346581A1 (de) 2004-07-22
DE10346581B4 true DE10346581B4 (de) 2007-12-27

Family

ID=32588500

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10346581A Expired - Fee Related DE10346581B4 (de) 2003-01-14 2003-10-07 Verfahren zum Herstellen einer Halbleitervorrichtung

Country Status (5)

Country Link
US (1) US6875672B2 (https=)
JP (1) JP4213478B2 (https=)
KR (1) KR100586865B1 (https=)
DE (1) DE10346581B4 (https=)
TW (1) TWI247393B (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
JP4072677B2 (ja) * 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP4528100B2 (ja) * 2004-11-25 2010-08-18 新光電気工業株式会社 半導体装置及びその製造方法
JP4698296B2 (ja) * 2005-06-17 2011-06-08 新光電気工業株式会社 貫通電極を有する半導体装置の製造方法
JP5193503B2 (ja) 2007-06-04 2013-05-08 新光電気工業株式会社 貫通電極付き基板及びその製造方法
JP4784641B2 (ja) * 2008-12-23 2011-10-05 株式会社デンソー 半導体装置およびその製造方法
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US9177893B2 (en) 2011-05-17 2015-11-03 Infineon Technologies Ag Semiconductor component with a front side and a back side metallization layer and manufacturing method thereof
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8558389B2 (en) 2011-12-08 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer
DE102013103723B4 (de) * 2013-04-12 2023-02-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines Bauteils
JP6557953B2 (ja) 2014-09-09 2019-08-14 大日本印刷株式会社 構造体及びその製造方法
JP7150632B2 (ja) * 2019-02-13 2022-10-11 キオクシア株式会社 半導体装置の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6474891A (en) * 1987-09-17 1989-03-20 Toshiba Corp Telephone exchange
EP0926726A1 (en) * 1997-12-16 1999-06-30 STMicroelectronics S.r.l. Fabrication process and electronic device having front-back through contacts for bonding onto boards
US6322903B1 (en) * 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6503778B1 (en) * 1999-09-28 2003-01-07 Sony Corporation Thin film device and method of manufacturing the same
EP1351288A1 (en) * 2002-04-05 2003-10-08 STMicroelectronics S.r.l. Process for manufacturing a through insulated interconnection in a body of semiconductor material

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4978639A (en) * 1989-01-10 1990-12-18 Avantek, Inc. Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
JP2839376B2 (ja) * 1991-02-05 1998-12-16 三菱電機株式会社 半導体装置の製造方法
US5447871A (en) * 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US5424245A (en) * 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
US5646067A (en) * 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
DE19543540C1 (de) * 1995-11-22 1996-11-21 Siemens Ag Vertikal integriertes Halbleiterbauelement mit zwei miteinander verbundenen Substraten und Herstellungsverfahren dafür
WO1998019337A1 (en) * 1996-10-29 1998-05-07 Trusi Technologies, Llc Integrated circuits and methods for their fabrication
JPH1074891A (ja) 1997-08-07 1998-03-17 Nec Corp 半導体装置
JP3184493B2 (ja) * 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
JP2001026326A (ja) 1999-07-14 2001-01-30 Ricoh Co Ltd 給紙分離装置
JP4035066B2 (ja) * 2003-02-04 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6474891A (en) * 1987-09-17 1989-03-20 Toshiba Corp Telephone exchange
EP0926726A1 (en) * 1997-12-16 1999-06-30 STMicroelectronics S.r.l. Fabrication process and electronic device having front-back through contacts for bonding onto boards
US6503778B1 (en) * 1999-09-28 2003-01-07 Sony Corporation Thin film device and method of manufacturing the same
US6322903B1 (en) * 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
EP1351288A1 (en) * 2002-04-05 2003-10-08 STMicroelectronics S.r.l. Process for manufacturing a through insulated interconnection in a body of semiconductor material

Also Published As

Publication number Publication date
TW200412657A (en) 2004-07-16
US6875672B2 (en) 2005-04-05
JP4213478B2 (ja) 2009-01-21
TWI247393B (en) 2006-01-11
US20040137705A1 (en) 2004-07-15
JP2004221240A (ja) 2004-08-05
KR100586865B1 (ko) 2006-06-07
DE10346581A1 (de) 2004-07-22
KR20040065142A (ko) 2004-07-21

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: TAIYO YUDEN CO., LTD., TOKIO/TOKYO, JP

Owner name: SHINKO ELECTRIC INDUSTRIES CO., LTD., NAGANO, JP

Owner name: SHARP K.K., OSAKA, JP

Owner name: RENESAS TECHNOLOGY CORP., TOKIO/TOKYO, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: TAIYO YUDEN CO., LTD., TOKIO/TOKYO, JP

Owner name: SHINKO ELECTRIC INDUSTRIES CO., LTD., NAGANO, JP

Owner name: SHARP K.K., OSAKA, JP

Owner name: RENESAS ELECTRONICS CORP., KAWASAKI-SHI, KANAG, JP

R081 Change of applicant/patentee

Owner name: RENESAS ELECTRONICS CORP., JP

Free format text: FORMER OWNERS: RENESAS ELECTRONICS CORP., KAWASAKI-SHI, KANAGAWA, JP; SHARP K.K., OSAKA, JP; SHINKO ELECTRIC INDUSTRIES CO., LTD., NAGANO, JP; TAIYO YUDEN CO., LTD., TOKIO/TOKYO, JP

Owner name: RENESAS ELECTRONICS CORP., KAWASAKI-SHI, JP

Free format text: FORMER OWNERS: RENESAS ELECTRONICS CORP., KAWASAKI-SHI, KANAGAWA, JP; SHARP K.K., OSAKA, JP; SHINKO ELECTRIC INDUSTRIES CO., LTD., NAGANO, JP; TAIYO YUDEN CO., LTD., TOKIO/TOKYO, JP

Owner name: SHINKO ELECTRIC INDUSTRIES CO., LTD., JP

Free format text: FORMER OWNERS: RENESAS ELECTRONICS CORP., KAWASAKI-SHI, KANAGAWA, JP; SHARP K.K., OSAKA, JP; SHINKO ELECTRIC INDUSTRIES CO., LTD., NAGANO, JP; TAIYO YUDEN CO., LTD., TOKIO/TOKYO, JP

Owner name: TAIYO YUDEN CO., LTD., JP

Free format text: FORMER OWNERS: RENESAS ELECTRONICS CORP., KAWASAKI-SHI, KANAGAWA, JP; SHARP K.K., OSAKA, JP; SHINKO ELECTRIC INDUSTRIES CO., LTD., NAGANO, JP; TAIYO YUDEN CO., LTD., TOKIO/TOKYO, JP

R082 Change of representative

Representative=s name: PRUEFER & PARTNER MBB PATENTANWAELTE RECHTSANW, DE

R081 Change of applicant/patentee

Owner name: RENESAS ELECTRONICS CORP., JP

Free format text: FORMER OWNERS: RENESAS ELECTRONICS CORP., KAWASAKI-SHI, KANAGAWA, JP; SHINKO ELECTRIC INDUSTRIES CO., LTD., NAGANO, JP; TAIYO YUDEN CO., LTD., TOKIO/TOKYO, JP

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Free format text: FORMER OWNERS: RENESAS ELECTRONICS CORP., KAWASAKI-SHI, KANAGAWA, JP; SHINKO ELECTRIC INDUSTRIES CO., LTD., NAGANO, JP; TAIYO YUDEN CO., LTD., TOKIO/TOKYO, JP

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Free format text: FORMER OWNERS: RENESAS ELECTRONICS CORP., KAWASAKI-SHI, KANAGAWA, JP; SHINKO ELECTRIC INDUSTRIES CO., LTD., NAGANO, JP; TAIYO YUDEN CO., LTD., TOKIO/TOKYO, JP

R082 Change of representative

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R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee