DE10309390A8 - Halbleiterspeichervorrichtung - Google Patents

Halbleiterspeichervorrichtung Download PDF

Info

Publication number
DE10309390A8
DE10309390A8 DE10309390A DE10309390A DE10309390A8 DE 10309390 A8 DE10309390 A8 DE 10309390A8 DE 10309390 A DE10309390 A DE 10309390A DE 10309390 A DE10309390 A DE 10309390A DE 10309390 A8 DE10309390 A8 DE 10309390A8
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10309390A
Other languages
English (en)
Other versions
DE10309390A1 (de
Inventor
Yasushi Nakashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE10309390A1 publication Critical patent/DE10309390A1/de
Publication of DE10309390A8 publication Critical patent/DE10309390A8/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/312—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
DE10309390A 2002-08-20 2003-03-04 Halbleiterspeichervorrichtung Withdrawn DE10309390A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002-239357 2002-08-20
JP2002239357A JP2004079843A (ja) 2002-08-20 2002-08-20 半導体記憶装置
JP02-239357 2002-08-20

Publications (2)

Publication Number Publication Date
DE10309390A1 DE10309390A1 (de) 2004-03-04
DE10309390A8 true DE10309390A8 (de) 2004-07-08

Family

ID=31492486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10309390A Withdrawn DE10309390A1 (de) 2002-08-20 2003-03-04 Halbleiterspeichervorrichtung

Country Status (6)

Country Link
US (1) US6765253B2 (de)
JP (1) JP2004079843A (de)
KR (1) KR20040017208A (de)
CN (1) CN1477641A (de)
DE (1) DE10309390A1 (de)
TW (1) TW200403673A (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4524735B2 (ja) 2003-06-20 2010-08-18 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP5470054B2 (ja) 2009-01-22 2014-04-16 株式会社半導体エネルギー研究所 半導体装置
US9443984B2 (en) * 2010-12-28 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
SG11201404871TA (en) * 2012-02-16 2014-09-26 Zeno Semiconductor Inc Memory cell comprising first and second transistors and methods of operating
US9515094B2 (en) 2013-06-26 2016-12-06 Semiconductor Energy Laboratory Co., Ltd. Storage device and semiconductor device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57171840A (en) * 1981-04-16 1982-10-22 Toshiba Corp Driving circuit
JPS60103587A (ja) * 1983-11-09 1985-06-07 Toshiba Corp 半導体記憶装置のメモリセルキヤパシタ電圧印加回路
JPS60226091A (ja) 1984-04-25 1985-11-11 Nec Corp 半導体記憶装置
DE3477973D1 (en) * 1984-08-02 1989-06-01 Siemens Ag Integrated write-read memory
US5194749A (en) * 1987-11-30 1993-03-16 Hitachi, Ltd. Semiconductor integrated circuit device
US5288377A (en) * 1991-06-05 1994-02-22 Macdermid, Incorporated Process for the manufacture of printed circuits using electrophoretically deposited organic resists
JP2983373B2 (ja) * 1992-02-25 1999-11-29 シャープ株式会社 スタティック型メモリセル
JPH05243528A (ja) 1992-02-26 1993-09-21 Sony Corp Ｓｒａｍメモリセル回路
JP2518133B2 (ja) * 1993-02-12 1996-07-24 日本電気株式会社 スタティック型半導体記憶装置
US5495437A (en) * 1994-07-05 1996-02-27 Motorola, Inc. Non-volatile RAM transferring data between ferro-electric capacitors and a memory cell
US5959598A (en) * 1995-07-20 1999-09-28 The Regents Of The University Of Colorado Pixel buffer circuits for implementing improved methods of displaying grey-scale or color images
US6130713A (en) * 1997-06-27 2000-10-10 Foveonics, Inc. CMOS active pixel cell with self reset for improved dynamic range
JP4552069B2 (ja) * 2001-01-04 2010-09-29 株式会社日立製作所 画像表示装置およびその駆動方法
US6434076B1 (en) * 2001-01-22 2002-08-13 International Business Machines Corporation Refresh control circuit for low-power SRAM applications
JP4837841B2 (ja) * 2001-06-12 2011-12-14 富士通セミコンダクター株式会社 スタティックｒａｍ
US6621727B2 (en) * 2002-01-04 2003-09-16 Kuo-Tso Chen Three-transistor SRAM device

Also Published As

Publication number Publication date
JP2004079843A (ja) 2004-03-11
DE10309390A1 (de) 2004-03-04
CN1477641A (zh) 2004-02-25
US20040036104A1 (en) 2004-02-26
KR20040017208A (ko) 2004-02-26
TW200403673A (en) 2004-03-01
US6765253B2 (en) 2004-07-20

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
OP8 Request for examination as to paragraph 44 patent law
8139 Disposal/non-payment of the annual fee