DE102020100101B8 - Verfahren zum ausbilden einer halbleitervorrichtungsstruktur - Google Patents

Verfahren zum ausbilden einer halbleitervorrichtungsstruktur Download PDF

Info

Publication number
DE102020100101B8
DE102020100101B8 DE102020100101.0A DE102020100101A DE102020100101B8 DE 102020100101 B8 DE102020100101 B8 DE 102020100101B8 DE 102020100101 A DE102020100101 A DE 102020100101A DE 102020100101 B8 DE102020100101 B8 DE 102020100101B8
Authority
DE
Germany
Prior art keywords
forming
semiconductor device
device structure
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE102020100101.0A
Other languages
English (en)
Other versions
DE102020100101B4 (de
DE102020100101A1 (de
Inventor
Kuo-Cheng Ching
Zhi-Chang Lin
Kuan-Ting Pan
Chih-Hao Wang
Shi-Ning Ju
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of DE102020100101A1 publication Critical patent/DE102020100101A1/de
Publication of DE102020100101B4 publication Critical patent/DE102020100101B4/de
Application granted granted Critical
Publication of DE102020100101B8 publication Critical patent/DE102020100101B8/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
DE102020100101.0A 2019-01-29 2020-01-06 Verfahren zum ausbilden einer halbleitervorrichtungsstruktur Active DE102020100101B8 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/260,483 2019-01-29
US16/260,483 US10825918B2 (en) 2019-01-29 2019-01-29 Semiconductor device structure and method for forming the same

Publications (3)

Publication Number Publication Date
DE102020100101A1 DE102020100101A1 (de) 2020-07-30
DE102020100101B4 DE102020100101B4 (de) 2023-06-01
DE102020100101B8 true DE102020100101B8 (de) 2023-08-17

Family

ID=71524766

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102020100101.0A Active DE102020100101B8 (de) 2019-01-29 2020-01-06 Verfahren zum ausbilden einer halbleitervorrichtungsstruktur

Country Status (5)

Country Link
US (4) US10825918B2 (de)
KR (1) KR102254863B1 (de)
CN (1) CN111490012B (de)
DE (1) DE102020100101B8 (de)
TW (1) TWI737136B (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10825918B2 (en) * 2019-01-29 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US11211381B2 (en) * 2019-01-29 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US11651965B2 (en) * 2019-08-12 2023-05-16 Tokyo Electron Limited Method and system for capping of cores for self-aligned multiple patterning
US11328963B2 (en) 2020-02-27 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and related methods
US11799019B2 (en) * 2020-02-27 2023-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Gate isolation feature and manufacturing method thereof
CN113130483A (zh) * 2020-02-27 2021-07-16 台湾积体电路制造股份有限公司 半导体结构
US20220037498A1 (en) * 2020-07-31 2022-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor Gate Structures and Methods of Forming the Same
US11329168B2 (en) * 2020-07-31 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with fish bone structure and methods of forming the same
DE102020131140A1 (de) * 2020-08-10 2022-02-10 Taiwan Semiconductor Manufacturing Co., Ltd. Gateisolierungsstruktur
US11728401B2 (en) 2020-10-30 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods thereof
US20220139914A1 (en) * 2020-10-30 2022-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device with Gate Isolation Structure and Method for Forming the Same
US11984356B2 (en) 2021-02-11 2024-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structures in semiconductor devices
US11848209B2 (en) 2021-02-26 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Patterning semiconductor devices and structures resulting therefrom
US11757024B2 (en) * 2021-04-07 2023-09-12 Taiwan Semiconductor Manufacturing Company Ltd. Etch selectivity control for epitaxy process window enlargement in semiconductor devices
US20220328627A1 (en) * 2021-04-08 2022-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and methods of forming the same
US11764277B2 (en) * 2021-06-04 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method for manufacturing the same
US20220399335A1 (en) * 2021-06-14 2022-12-15 Intel Corporation Integrated circuit structures with backside gate partial cut or trench contact partial cut

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9601492B1 (en) 2015-11-16 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices and methods of forming the same
US20170256457A1 (en) 2016-03-04 2017-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
WO2018004680A1 (en) 2016-07-01 2018-01-04 Intel Corporation Self-aligned gate edge trigate and finfet devices
WO2018182617A1 (en) 2017-03-30 2018-10-04 Intel Corporation Transistors employing non-selective deposition of source/drain material

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100639220B1 (ko) * 2005-12-01 2006-11-01 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
JP2013038213A (ja) * 2011-08-08 2013-02-21 Toshiba Corp 集積回路装置及びその製造方法
US9287179B2 (en) * 2012-01-19 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Composite dummy gate with conformal polysilicon layer for FinFET device
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9006829B2 (en) 2012-08-24 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Aligned gate-all-around structure
CN103839819A (zh) * 2012-11-25 2014-06-04 中国科学院微电子研究所 半导体器件及其制造方法
US9209247B2 (en) 2013-05-10 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned wrapped-around structure
US9147612B2 (en) * 2013-11-25 2015-09-29 United Microelectronics Corp. Method for forming a semiconductor structure
US9136332B2 (en) 2013-12-10 2015-09-15 Taiwan Semiconductor Manufacturing Company Limited Method for forming a nanowire field effect transistor device having a replacement gate
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
WO2015094305A1 (en) 2013-12-19 2015-06-25 Intel Corporation Self-aligned gate edge and local interconnect and method to fabricate same
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9306038B1 (en) * 2014-12-12 2016-04-05 International Business Machines Corporation Shallow extension junction
US9412817B2 (en) 2014-12-19 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide regions in vertical gate all around (VGAA) devices and methods of forming same
US9536738B2 (en) 2015-02-13 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical gate all around (VGAA) devices and methods of manufacturing the same
US9502265B1 (en) 2015-11-04 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical gate all around (VGAA) transistors and methods of forming the same
US9520482B1 (en) * 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US10217817B2 (en) * 2016-01-27 2019-02-26 International Business Machines Corporation Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs
US9786765B2 (en) 2016-02-16 2017-10-10 Globalfoundries Inc. FINFET having notched fins and method of forming same
US10522417B2 (en) * 2017-04-27 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with different liners for PFET and NFET and method of fabricating thereof
CN108807532B (zh) * 2017-04-28 2021-07-06 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US10211302B2 (en) * 2017-06-28 2019-02-19 International Business Machines Corporation Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts
US10403714B2 (en) * 2017-08-29 2019-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Fill fins for semiconductor devices
US20190081145A1 (en) * 2017-09-12 2019-03-14 Globalfoundries Inc. Contact to source/drain regions and method of forming same
US10453752B2 (en) * 2017-09-18 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a gate-all-around semiconductor device
US10971391B2 (en) * 2018-06-13 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric gap fill
US10665514B2 (en) * 2018-06-19 2020-05-26 International Business Machines Corporation Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal
US10573755B1 (en) 2018-09-12 2020-02-25 International Business Machines Corporation Nanosheet FET with box isolation on substrate
US10825918B2 (en) * 2019-01-29 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US11211381B2 (en) * 2019-01-29 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US11532723B2 (en) 2019-10-29 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-end gate structures and method forming same
US11545490B2 (en) 2019-12-17 2023-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for forming the same
US11799019B2 (en) * 2020-02-27 2023-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Gate isolation feature and manufacturing method thereof
US11349004B2 (en) * 2020-04-28 2022-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Backside vias in semiconductor device
US11424347B2 (en) * 2020-06-11 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11322505B2 (en) * 2020-06-30 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Ferroelectric random access memory devices and methods
US20220037498A1 (en) * 2020-07-31 2022-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor Gate Structures and Methods of Forming the Same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9601492B1 (en) 2015-11-16 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices and methods of forming the same
US20170256457A1 (en) 2016-03-04 2017-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
WO2018004680A1 (en) 2016-07-01 2018-01-04 Intel Corporation Self-aligned gate edge trigate and finfet devices
WO2018182617A1 (en) 2017-03-30 2018-10-04 Intel Corporation Transistors employing non-selective deposition of source/drain material

Also Published As

Publication number Publication date
US20200243665A1 (en) 2020-07-30
US20210226036A1 (en) 2021-07-22
US11502187B2 (en) 2022-11-15
TWI737136B (zh) 2021-08-21
TW202101546A (zh) 2021-01-01
US11004959B2 (en) 2021-05-11
US10825918B2 (en) 2020-11-03
US20200243666A1 (en) 2020-07-30
CN111490012A (zh) 2020-08-04
CN111490012B (zh) 2023-07-14
KR102254863B1 (ko) 2021-05-26
US20230053451A1 (en) 2023-02-23
DE102020100101B4 (de) 2023-06-01
DE102020100101A1 (de) 2020-07-30
KR20200094679A (ko) 2020-08-07

Similar Documents

Publication Publication Date Title
DE102020100101B8 (de) Verfahren zum ausbilden einer halbleitervorrichtungsstruktur
DE102016226235A8 (de) Siliziumcarbid-halbleitervorrichtung und verfahren zum herstellen einer siliziumcarbid-halbleitervorrichtung
DE112016003158A5 (de) Reinigungseinrichtung sowie Verfahren zum Reinigen einer Fläche
GB201801337D0 (en) Method for etching a semiconductor structure
DE112015003254T8 (de) Halbleiterstapelstruktur und Verfahren und Einrichtung zum Separieren einer Nitridhalbleiterschicht unter Verwendung derselben
DE112019000282A5 (de) Verfahren zum herstellen eines linsenelementes
DE102016105735B8 (de) Verfahren zur Ausbildung eines Verdrahtungsmusters
DE102016107953A8 (de) Halbleiterbauelemente und Verfahren zum Testen einer Gate-Isolierung einer Transistorstruktur
DE112018002082A5 (de) Verfahren und Vorrichtung zum Ausbilden einer Schicht auf einem Halbleitersubstrat sowie Halbleitersubstrat
DE112017000938T8 (de) Verfahren zum Reinigen eines Halbleiterwafers
DE112013006790B8 (de) Halbleitervorrichtungen und Verfahren zum Herstellen einer Halbleitervorrichtung
DE102016112066A8 (de) Verfahren zum formen einer metallplatte und gerät zum formen einer metallplatte
DE112017007232A5 (de) Verfahren zum Betreiben einer Dampferzeugungsvorrichtung
DE102016111940A8 (de) Verfahren zum Herstellen einer Superjunction-Halbleitervorrichtung und Superjunction-Halbleitervorrichtung
DE112017000834A5 (de) Verfahren zum Betreiben einer Halbleiterlichtquelle und Halbleiterlichtquelle
IL261919A (en) A bottom-up method for creating wire structures on a substrate
DE112019006189A5 (de) Brennervorrichtung und verfahren zum betreiben einer brennervorrichtung
DE112013004761A5 (de) Verfahren zum Vereinzeln von Bereichen einer Halbleiterschicht
DE112017003171A5 (de) Verfahren zum Ermitteln einer Zeit
DE112019000384A5 (de) Verfahren zum steuern eines stromes einer leuchtdiode
DE112018007486A5 (de) Verfahren zum Herstellen einer Kontaktierungseinrichtung
DE112016002040A5 (de) Verfahren zum herstellen eines konverterbauteils
DE112015006283A5 (de) Magnetostriktive Wegmessvorrichtung und Verfahren zum Betreiben einer magnetostriktiven Wegmessvorrichtung
DE112018000979A5 (de) Verfahren zum Betreiben einer Beleuchtungseinrichtung
DE102014108873A8 (de) Verfahren zum Bestimmen einer aktuellen Position einer Landeeinrichtung

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R130 Divisional application to

Ref document number: 102020008231

Country of ref document: DE

R083 Amendment of/additions to inventor(s)
R020 Patent grant now final