DE102018127379A8 - Ein zum Reduzieren einer Schreiblatenz fähiges Verfahren zum Betreiben einer resistiven Speichervorrichtung - Google Patents

Ein zum Reduzieren einer Schreiblatenz fähiges Verfahren zum Betreiben einer resistiven Speichervorrichtung Download PDF

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Publication number
DE102018127379A8
DE102018127379A8 DE102018127379.7A DE102018127379A DE102018127379A8 DE 102018127379 A8 DE102018127379 A8 DE 102018127379A8 DE 102018127379 A DE102018127379 A DE 102018127379A DE 102018127379 A8 DE102018127379 A8 DE 102018127379A8
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DE
Germany
Prior art keywords
operating
memory device
resistive memory
write latency
reducing write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102018127379.7A
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English (en)
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DE102018127379A1 (de
Inventor
Hye-Young Ryu
Kyung-Chang Ryoo
Jong-jun Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102018127379A1 publication Critical patent/DE102018127379A1/de
Publication of DE102018127379A8 publication Critical patent/DE102018127379A8/de
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0023Address circuits or decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0023Address circuits or decoders
    • G11C13/0028Word-line or row circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0061Timing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • G11C2013/0076Write operation performed depending on read result
DE102018127379.7A 2018-02-27 2018-11-02 Ein zum Reduzieren einer Schreiblatenz fähiges Verfahren zum Betreiben einerresistiven Speichervorrichtung Pending DE102018127379A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2018-0023899 2018-02-27
KR1020180023899A KR102452623B1 (ko) 2018-02-27 2018-02-27 기입 레이턴시를 줄일 수 있는 저항성 메모리 장치의 동작 방법

Publications (2)

Publication Number Publication Date
DE102018127379A1 DE102018127379A1 (de) 2019-08-29
DE102018127379A8 true DE102018127379A8 (de) 2019-12-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE102018127379.7A Pending DE102018127379A1 (de) 2018-02-27 2018-11-02 Ein zum Reduzieren einer Schreiblatenz fähiges Verfahren zum Betreiben einerresistiven Speichervorrichtung

Country Status (4)

Country Link
US (1) US10629262B2 (de)
KR (1) KR102452623B1 (de)
CN (1) CN110197687A (de)
DE (1) DE102018127379A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210081049A (ko) * 2019-12-23 2021-07-01 에스케이하이닉스 주식회사 저항성 메모리 장치 및 그의 동작 방법

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* Cited by examiner, † Cited by third party
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KR100827702B1 (ko) 2006-11-01 2008-05-07 삼성전자주식회사 가변저항 반도체 메모리 장치
JP4309421B2 (ja) 2006-12-25 2009-08-05 エルピーダメモリ株式会社 半導体記憶装置とその書き込み制御方法
KR100819061B1 (ko) * 2007-03-06 2008-04-03 한국전자통신연구원 쓰기 전력 계산 및 데이터 반전 기능을 통한 상 변화메모리에서의 데이터 쓰기 장치 및 방법
US8332575B2 (en) * 2007-06-20 2012-12-11 Samsung Electronics Co., Ltd. Data management systems, methods and computer program products using a phase-change random access memory for selective data maintenance
DE102007036989B4 (de) 2007-08-06 2015-02-26 Qimonda Ag Verfahren zum Betrieb einer Speichervorrichtung, Speichereinrichtung und Speichervorrichtung
KR20090016195A (ko) * 2007-08-10 2009-02-13 주식회사 하이닉스반도체 상 변화 메모리 장치
KR101411499B1 (ko) * 2008-05-19 2014-07-01 삼성전자주식회사 가변 저항 메모리 장치 및 그것의 관리 방법
JP5474327B2 (ja) * 2008-10-02 2014-04-16 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置及びこれを備えるデータ処理システム
US9208835B2 (en) 2009-12-29 2015-12-08 Micron Technology, Inc. Timing violation handling in a synchronous interface memory
US8184487B2 (en) 2010-08-30 2012-05-22 Micron Technology, Inc. Modified read operation for non-volatile memory
KR20130134608A (ko) * 2012-05-31 2013-12-10 에스케이하이닉스 주식회사 가변 저항 메모리 장치 및 그것을 포함하는 데이터 저장 장치
WO2014013595A1 (ja) * 2012-07-19 2014-01-23 株式会社日立製作所 半導体装置
CN102831929B (zh) * 2012-09-04 2015-07-22 中国科学院上海微系统与信息技术研究所 一种相变存储器的读写转换系统及方法
WO2014058994A2 (en) 2012-10-11 2014-04-17 Everspin Technologies, Inc. Memory device with timing overlap mode
CN104142892B (zh) * 2013-05-09 2017-08-11 华为技术有限公司 一种数据读写方法、装置及系统
KR20150020477A (ko) 2013-08-16 2015-02-26 삼성전자주식회사 메모리 장치, 이를 포함하는 메모리 시스템 및 그 동작 방법
KR20150044475A (ko) * 2013-10-16 2015-04-27 에스케이하이닉스 주식회사 저항성 메모리 장치 및 동작 방법 방법과 이를 포함하는 시스템
US9239788B2 (en) * 2013-10-24 2016-01-19 Qualcomm Incorporated Split write operation for resistive memory cache
FR3015103B1 (fr) * 2013-12-12 2017-05-26 Commissariat Energie Atomique Systeme d'ecriture de donnees dans une memoire
KR102144779B1 (ko) * 2014-02-04 2020-08-14 삼성전자 주식회사 저항체를 이용한 비휘발성 메모리 장치의 구동 방법
US9257167B2 (en) 2014-03-13 2016-02-09 Katsuyuki Fujita Resistance change memory
KR102131324B1 (ko) * 2014-07-08 2020-07-07 삼성전자 주식회사 저항성 메모리 장치 및 저항성 메모리 장치의 동작방법
US20170229176A1 (en) * 2014-09-19 2017-08-10 Hitach, Ltd. Semiconductor storage device, and storage device using same
KR20170055786A (ko) 2015-11-12 2017-05-22 삼성전자주식회사 데이터 기입 및 독출 레이턴시를 제어하는 레이턴시 제어 회로를 갖는 메모리 장치
US9761306B1 (en) 2016-03-08 2017-09-12 Toshiba Memory Corporation Resistive memory device and method of programming the same
US9859003B1 (en) * 2016-10-26 2018-01-02 Arm Limited Selective writes in a storage element

Also Published As

Publication number Publication date
US20190267084A1 (en) 2019-08-29
KR102452623B1 (ko) 2022-10-07
DE102018127379A1 (de) 2019-08-29
CN110197687A (zh) 2019-09-03
KR20190102870A (ko) 2019-09-04
US10629262B2 (en) 2020-04-21

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