DE102013103100B4 - Verfahren zum Ablösen eines Halbleiterchips von einer Folie - Google Patents

Verfahren zum Ablösen eines Halbleiterchips von einer Folie Download PDF

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Publication number
DE102013103100B4
DE102013103100B4 DE102013103100.5A DE102013103100A DE102013103100B4 DE 102013103100 B4 DE102013103100 B4 DE 102013103100B4 DE 102013103100 A DE102013103100 A DE 102013103100A DE 102013103100 B4 DE102013103100 B4 DE 102013103100B4
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Germany
Prior art keywords
plates
lowered
chip
carrier
cover plate
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Expired - Fee Related
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DE102013103100.5A
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German (de)
English (en)
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DE102013103100A1 (de
Inventor
Ernst Barmettler
Fabian Hurschler
Brian Pulis
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Besi Switzerland AG
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Besi Switzerland AG
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Publication of DE102013103100A1 publication Critical patent/DE102013103100A1/de
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Publication of DE102013103100B4 publication Critical patent/DE102013103100B4/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10S156/918—Delaminating processes adapted for specified product, e.g. delaminating medical specimen slide
    • Y10S156/93—Semiconductive product delaminating, e.g. delaminating emiconductive wafer from underlayer
    • Y10S156/931—Peeling away backing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10S156/918—Delaminating processes adapted for specified product, e.g. delaminating medical specimen slide
    • Y10S156/93—Semiconductive product delaminating, e.g. delaminating emiconductive wafer from underlayer
    • Y10S156/931—Peeling away backing
    • Y10S156/932—Peeling away backing with poking during delaminating, e.g. jabbing release sheet backing to remove wafer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10S156/934—Apparatus having delaminating means adapted for delaminating a specified article
    • Y10S156/941—Means for delaminating semiconductive product
    • Y10S156/943—Means for delaminating semiconductive product with poking delaminating means, e.g. jabbing means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/11—Methods of delaminating, per se; i.e., separating at bonding face
    • Y10T156/1168—Gripping and pulling work apart during delaminating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/11—Methods of delaminating, per se; i.e., separating at bonding face
    • Y10T156/1168—Gripping and pulling work apart during delaminating
    • Y10T156/1179—Gripping and pulling work apart during delaminating with poking during delaminating [e.g., jabbing, etc.]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/19—Delaminating means
    • Y10T156/1978—Delaminating bending means
    • Y10T156/1983—Poking delaminating means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)
DE102013103100.5A 2012-03-30 2013-03-26 Verfahren zum Ablösen eines Halbleiterchips von einer Folie Expired - Fee Related DE102013103100B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH453/12 2012-03-30
CH00453/12A CH706280B1 (de) 2012-03-30 2012-03-30 Verfahren zum Ablösen eines Halbleiterchips von einer Folie.

Publications (2)

Publication Number Publication Date
DE102013103100A1 DE102013103100A1 (de) 2013-10-02
DE102013103100B4 true DE102013103100B4 (de) 2024-02-29

Family

ID=49154876

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102013103100.5A Expired - Fee Related DE102013103100B4 (de) 2012-03-30 2013-03-26 Verfahren zum Ablösen eines Halbleiterchips von einer Folie

Country Status (10)

Country Link
US (1) US9039867B2 (cg-RX-API-DMAC7.html)
JP (1) JP6128459B2 (cg-RX-API-DMAC7.html)
KR (1) KR102084792B1 (cg-RX-API-DMAC7.html)
CN (1) CN103367136B (cg-RX-API-DMAC7.html)
CH (1) CH706280B1 (cg-RX-API-DMAC7.html)
DE (1) DE102013103100B4 (cg-RX-API-DMAC7.html)
FR (1) FR2988902B1 (cg-RX-API-DMAC7.html)
MY (1) MY164119A (cg-RX-API-DMAC7.html)
SG (1) SG193709A1 (cg-RX-API-DMAC7.html)
TW (1) TWI569338B (cg-RX-API-DMAC7.html)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH707236B1 (de) 2012-11-23 2016-10-31 Besi Switzerland Ag Verfahren zum Ablösen von Halbleiterchips von einer Folie.
JP5717910B1 (ja) * 2014-02-26 2015-05-13 株式会社新川 半導体ダイのピックアップ装置及びピックアップ方法
SG10201403372SA (en) * 2014-06-18 2016-01-28 Mfg Integration Technology Ltd System and method for peeling a semiconductor chip from a tape using a multistage ejector
JP6797569B2 (ja) * 2016-06-13 2020-12-09 ファスフォードテクノロジ株式会社 半導体製造装置および半導体装置の製造方法
TWI648213B (zh) * 2017-11-30 2019-01-21 景碩科技股份有限公司 撕箔機構
JP2019169516A (ja) * 2018-03-22 2019-10-03 東芝メモリ株式会社 半導体装置の突き上げ装置及び突き上げ方法
CN109192681B (zh) * 2018-09-01 2022-05-31 佛山市美特智能科技有限公司 芯片的快速柔性制造系统
JP7217605B2 (ja) * 2018-09-21 2023-02-03 ファスフォードテクノロジ株式会社 半導体製造装置、突上げ治具および半導体装置の製造方法
CH715447B1 (de) 2018-10-15 2022-01-14 Besi Switzerland Ag Chip-Auswerfer.
DE102018125682B4 (de) * 2018-10-16 2023-01-19 Asm Assembly Systems Gmbh & Co. Kg Ejektorvorrichtung sowie Verfahren zum Unterstützen eines Ablösens eines auf einer Haltefolie angeordneten elektrischen Bauteils
KR102656718B1 (ko) * 2018-11-05 2024-04-12 세메스 주식회사 다이 이젝팅 장치
JP7274902B2 (ja) * 2019-03-25 2023-05-17 ファスフォードテクノロジ株式会社 半導体製造装置および半導体装置の製造方法
KR102020034B1 (ko) * 2019-07-09 2019-09-10 (주)삼정오토메이션 적층세라믹콘덴서 취출 방법
KR102177863B1 (ko) * 2020-08-07 2020-11-11 변영기 칩 필름 단계적 박리장치
JP7039675B2 (ja) * 2020-11-18 2022-03-22 ファスフォードテクノロジ株式会社 半導体製造装置および半導体装置の製造方法
US11764098B2 (en) * 2021-04-16 2023-09-19 Asmpt Singapore Pte. Ltd. Detaching a die from an adhesive tape by air ejection
JP7645768B2 (ja) * 2021-10-26 2025-03-14 三菱電機株式会社 半導体製造装置および半導体装置の製造方法
US12444625B2 (en) 2021-12-08 2025-10-14 Samsung Electronics Co., Ltd. Chip peeling apparatus and chip peeling method using the same
JP7787014B2 (ja) 2022-05-11 2025-12-16 三星電子株式会社 チップ剥離装置及びチップ剥離方法
CN119176305A (zh) * 2023-06-21 2024-12-24 纬创资通(重庆)有限公司 除膜设备与揭膜机构
KR102819732B1 (ko) 2023-11-28 2025-06-16 한국생산기술연구원 반도체 제조 공정에서의 다이 이젝팅 방법 및 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115482B2 (en) 2003-09-17 2006-10-03 Renesas Technology Corp. Method of manufacturing semiconductor device
EP2184765A1 (de) 2008-11-05 2010-05-12 Esec AG Chip-Auswerfer
US20100252205A1 (en) 2009-04-02 2010-10-07 Man Wai Chan Device for thin die detachment and pick-up
US8092645B2 (en) 2010-02-05 2012-01-10 Asm Assembly Automation Ltd Control and monitoring system for thin die detachment and pick-up

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3976541B2 (ja) 2001-10-23 2007-09-19 富士通株式会社 半導体チップの剥離方法及び装置
CH697213A5 (de) * 2004-05-19 2008-06-25 Alphasem Ag Verfahren und Vorrichtung zum Ablösen eines auf eine flexible Folie geklebten Bauteils.
JP4735829B2 (ja) * 2005-12-06 2011-07-27 澁谷工業株式会社 チップ突き上げ装置
US7665204B2 (en) * 2006-10-16 2010-02-23 Asm Assembly Automation Ltd. Die detachment apparatus comprising pre-peeling structure
JP4693805B2 (ja) * 2007-03-16 2011-06-01 株式会社東芝 半導体装置の製造装置及び製造方法
TWI463580B (zh) 2007-06-19 2014-12-01 瑞薩科技股份有限公司 Manufacturing method of semiconductor integrated circuit device
JP4864816B2 (ja) * 2007-06-19 2012-02-01 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP2011216529A (ja) * 2010-03-31 2011-10-27 Furukawa Electric Co Ltd:The 半導体装置の製造方法
CH707236B1 (de) * 2012-11-23 2016-10-31 Besi Switzerland Ag Verfahren zum Ablösen von Halbleiterchips von einer Folie.

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115482B2 (en) 2003-09-17 2006-10-03 Renesas Technology Corp. Method of manufacturing semiconductor device
EP2184765A1 (de) 2008-11-05 2010-05-12 Esec AG Chip-Auswerfer
US20100252205A1 (en) 2009-04-02 2010-10-07 Man Wai Chan Device for thin die detachment and pick-up
US8092645B2 (en) 2010-02-05 2012-01-10 Asm Assembly Automation Ltd Control and monitoring system for thin die detachment and pick-up

Also Published As

Publication number Publication date
DE102013103100A1 (de) 2013-10-02
KR102084792B1 (ko) 2020-03-04
TW201401384A (zh) 2014-01-01
CH706280A1 (de) 2013-09-30
US9039867B2 (en) 2015-05-26
CH706280B1 (de) 2016-03-15
FR2988902A1 (fr) 2013-10-04
US20130255889A1 (en) 2013-10-03
CN103367136B (zh) 2017-08-25
TWI569338B (zh) 2017-02-01
KR20130111366A (ko) 2013-10-10
JP6128459B2 (ja) 2017-05-17
MY164119A (en) 2017-11-30
SG193709A1 (en) 2013-10-30
FR2988902B1 (fr) 2016-12-30
JP2013214739A (ja) 2013-10-17
CN103367136A (zh) 2013-10-23

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