DE102011122918B3 - Halbleitervorrichtung - Google Patents

Halbleitervorrichtung Download PDF

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Publication number
DE102011122918B3
DE102011122918B3 DE102011122918.7A DE102011122918A DE102011122918B3 DE 102011122918 B3 DE102011122918 B3 DE 102011122918B3 DE 102011122918 A DE102011122918 A DE 102011122918A DE 102011122918 B3 DE102011122918 B3 DE 102011122918B3
Authority
DE
Germany
Prior art keywords
wafer
main surface
region
circuit pattern
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102011122918.7A
Other languages
German (de)
English (en)
Inventor
Yoshihiro Tsukahara
Shinsuke Watanabe
Ko Kanaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE102011122918B3 publication Critical patent/DE102011122918B3/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE102011122918.7A 2010-07-29 2011-07-13 Halbleitervorrichtung Expired - Fee Related DE102011122918B3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010170570A JP5521862B2 (ja) 2010-07-29 2010-07-29 半導体装置の製造方法
JP2010-170570 2010-07-29

Publications (1)

Publication Number Publication Date
DE102011122918B3 true DE102011122918B3 (de) 2016-05-19

Family

ID=45525895

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102011122918.7A Expired - Fee Related DE102011122918B3 (de) 2010-07-29 2011-07-13 Halbleitervorrichtung
DE102011079105A Withdrawn DE102011079105A1 (de) 2010-07-29 2011-07-13 Halbleitervorrichtung und Verfahren zum Herstellen derselben

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE102011079105A Withdrawn DE102011079105A1 (de) 2010-07-29 2011-07-13 Halbleitervorrichtung und Verfahren zum Herstellen derselben

Country Status (5)

Country Link
US (1) US8728866B2 (https=)
JP (1) JP5521862B2 (https=)
CN (1) CN102347243B (https=)
DE (2) DE102011122918B3 (https=)
TW (1) TWI446429B (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428255B (zh) * 2013-03-29 2019-02-15 日月光半导体制造股份有限公司 透光壳体及其制造方法与应用其的光学组件
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
JP6221736B2 (ja) * 2013-12-25 2017-11-01 三菱電機株式会社 半導体装置
JP6215755B2 (ja) * 2014-04-14 2017-10-18 ルネサスエレクトロニクス株式会社 半導体装置
TWI566288B (zh) * 2014-07-14 2017-01-11 矽品精密工業股份有限公司 切割用載具及切割方法
JP6314731B2 (ja) 2014-08-01 2018-04-25 株式会社ソシオネクスト 半導体装置及び半導体装置の製造方法
US10277271B2 (en) 2015-07-28 2019-04-30 Nippon Telegraph And Telephone Corporation Optical module
WO2017029822A1 (ja) * 2015-08-18 2017-02-23 三菱電機株式会社 半導体装置
US10393532B2 (en) * 2015-10-20 2019-08-27 International Business Machines Corporation Emergency responsive navigation
JP6935807B2 (ja) * 2017-02-02 2021-09-15 昭和電工マテリアルズ株式会社 電子部品の製造方法、仮保護用樹脂組成物及び仮保護用樹脂フィルム
JP2019192729A (ja) * 2018-04-23 2019-10-31 株式会社村田製作所 半導体装置
CN112189251B (zh) * 2018-05-28 2023-12-26 三菱电机株式会社 半导体装置的制造方法
JP7034105B2 (ja) * 2019-01-18 2022-03-11 三菱電機株式会社 電力用半導体装置の製造方法、電力用半導体装置および電力変換装置
KR102785840B1 (ko) 2019-12-13 2025-03-26 삼성전자주식회사 반도체 패키지
US11948893B2 (en) 2021-12-21 2024-04-02 Qorvo Us, Inc. Electronic component with lid to manage radiation feedback

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080081398A1 (en) * 2006-10-02 2008-04-03 Fionix Inc. Cap Wafer for Wafer Bonded Packaging and Method for Manufacturing the Same

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EP0544329A3 (en) 1991-11-28 1993-09-01 Kabushiki Kaisha Toshiba Semiconductor package
JP2501279B2 (ja) 1991-11-29 1996-05-29 株式会社東芝 半導体パッケ―ジ
JP2001024079A (ja) 1999-07-05 2001-01-26 Seiko Epson Corp 電子部品の封止構造
US7026223B2 (en) 2002-03-28 2006-04-11 M/A-Com, Inc Hermetic electric component package
JP4342174B2 (ja) 2002-12-27 2009-10-14 新光電気工業株式会社 電子デバイス及びその製造方法
JP2005057136A (ja) 2003-08-06 2005-03-03 Matsushita Electric Ind Co Ltd 半導体装置
JP4312631B2 (ja) 2004-03-03 2009-08-12 三菱電機株式会社 ウエハレベルパッケージ構造体とその製造方法、及びそのウエハレベルパッケージ構造体から分割された素子
JP4993848B2 (ja) * 2004-05-28 2012-08-08 三洋電機株式会社 配線基材
KR100594716B1 (ko) 2004-07-27 2006-06-30 삼성전자주식회사 공동부를 구비한 캡 웨이퍼, 이를 이용한 반도체 칩, 및그 제조방법
FR2879889B1 (fr) 2004-12-20 2007-01-26 United Monolithic Semiconduct Boitier miniature hyperfrequence et procede de fabrication du boitier
CN100514591C (zh) * 2005-03-02 2009-07-15 皇家飞利浦电子股份有限公司 半导体封装的制造方法及所制成的封装
US7495462B2 (en) 2005-03-24 2009-02-24 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes
JP2007005948A (ja) * 2005-06-22 2007-01-11 Alps Electric Co Ltd 電子部品及びその製造方法
US20070004079A1 (en) 2005-06-30 2007-01-04 Geefay Frank S Method for making contact through via contact to an offset contactor inside a cap for the wafer level packaging of FBAR chips
JP2007019107A (ja) * 2005-07-05 2007-01-25 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
KR100752713B1 (ko) * 2005-10-10 2007-08-29 삼성전기주식회사 이미지센서의 웨이퍼 레벨 칩 스케일 패키지 및 그제조방법
US7393758B2 (en) * 2005-11-03 2008-07-01 Maxim Integrated Products, Inc. Wafer level packaging process
JP4860552B2 (ja) 2007-06-08 2012-01-25 日本オプネクスト株式会社 半導体装置
JP5344336B2 (ja) * 2008-02-27 2013-11-20 株式会社ザイキューブ 半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080081398A1 (en) * 2006-10-02 2008-04-03 Fionix Inc. Cap Wafer for Wafer Bonded Packaging and Method for Manufacturing the Same

Also Published As

Publication number Publication date
CN102347243A (zh) 2012-02-08
CN102347243B (zh) 2014-08-20
DE102011079105A1 (de) 2012-04-12
TW201205656A (en) 2012-02-01
JP2012033615A (ja) 2012-02-16
US20120025366A1 (en) 2012-02-02
TWI446429B (zh) 2014-07-21
US8728866B2 (en) 2014-05-20
JP5521862B2 (ja) 2014-06-18

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