DE102008034346B4 - Verfahren zum Zugriff auf einen Speicherchip - Google Patents

Verfahren zum Zugriff auf einen Speicherchip Download PDF

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Publication number
DE102008034346B4
DE102008034346B4 DE200810034346 DE102008034346A DE102008034346B4 DE 102008034346 B4 DE102008034346 B4 DE 102008034346B4 DE 200810034346 DE200810034346 DE 200810034346 DE 102008034346 A DE102008034346 A DE 102008034346A DE 102008034346 B4 DE102008034346 B4 DE 102008034346B4
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Germany
Prior art keywords
pin
input
memory
column address
column
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DE200810034346
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German (de)
English (en)
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DE102008034346A1 (de
Inventor
Chih-Hui Yeh
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Nanya Technology Corp
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Nanya Technology Corp
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Publication of DE102008034346A1 publication Critical patent/DE102008034346A1/de
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Publication of DE102008034346B4 publication Critical patent/DE102008034346B4/de
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry

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  • Dram (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Computer Hardware Design (AREA)
DE200810034346 2008-01-21 2008-07-23 Verfahren zum Zugriff auf einen Speicherchip Active DE102008034346B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW97102177A TW200933645A (en) 2008-01-21 2008-01-21 Method for accessing memory chip
TW097102177 2008-01-21

Publications (2)

Publication Number Publication Date
DE102008034346A1 DE102008034346A1 (de) 2009-07-30
DE102008034346B4 true DE102008034346B4 (de) 2014-10-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE200810034346 Active DE102008034346B4 (de) 2008-01-21 2008-07-23 Verfahren zum Zugriff auf einen Speicherchip

Country Status (4)

Country Link
JP (1) JP4699498B2 (ko)
KR (1) KR100951605B1 (ko)
DE (1) DE102008034346B4 (ko)
TW (1) TW200933645A (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102542584B1 (ko) * 2016-03-11 2023-06-14 에스케이하이닉스 주식회사 반도체 메모리의 입력 장치 및 이를 포함하는 반도체 메모리 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870350A (en) * 1997-05-21 1999-02-09 International Business Machines Corporation High performance, high bandwidth memory bus architecture utilizing SDRAMs
US6067632A (en) * 1998-01-06 2000-05-23 Fujitsu Limited Clock-synchronized memory device and the scheduler thereof
US6236251B1 (en) * 1998-03-04 2001-05-22 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit with multiple selectively activated synchronization circuits

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01144664A (ja) * 1988-03-01 1989-06-06 Mitsubishi Electric Corp 半導体メモリ用集積回路装置
JPH05274877A (ja) * 1992-03-25 1993-10-22 Mitsubishi Electric Corp 半導体記憶装置
JPH09213092A (ja) * 1996-02-08 1997-08-15 Hitachi Ltd 半導体集積回路装置
US5805520A (en) 1997-04-25 1998-09-08 Hewlett-Packard Company Integrated circuit address reconfigurability
JPH11317080A (ja) * 1998-03-04 1999-11-16 Matsushita Electric Ind Co Ltd 半導体集積回路
KR100336573B1 (ko) * 1999-11-30 2002-05-16 박종섭 램버스 디램
JP2006294074A (ja) * 2005-03-14 2006-10-26 Fujitsu Ltd 半導体記憶装置
KR100671747B1 (ko) * 2006-01-04 2007-01-19 삼성전자주식회사 개선된 애디티브 레이턴시를 가진 메모리 시스템 및제어방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870350A (en) * 1997-05-21 1999-02-09 International Business Machines Corporation High performance, high bandwidth memory bus architecture utilizing SDRAMs
US6067632A (en) * 1998-01-06 2000-05-23 Fujitsu Limited Clock-synchronized memory device and the scheduler thereof
US6236251B1 (en) * 1998-03-04 2001-05-22 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit with multiple selectively activated synchronization circuits

Also Published As

Publication number Publication date
KR100951605B1 (ko) 2010-04-09
JP2009176398A (ja) 2009-08-06
TW200933645A (en) 2009-08-01
KR20090080463A (ko) 2009-07-24
JP4699498B2 (ja) 2011-06-08
DE102008034346A1 (de) 2009-07-30

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