DE102007010882B4 - Verfahren zur Herstellung einer Lötverbindung zwischen einem Halbleiterchip und einem Substrat - Google Patents

Verfahren zur Herstellung einer Lötverbindung zwischen einem Halbleiterchip und einem Substrat Download PDF

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Publication number
DE102007010882B4
DE102007010882B4 DE102007010882A DE102007010882A DE102007010882B4 DE 102007010882 B4 DE102007010882 B4 DE 102007010882B4 DE 102007010882 A DE102007010882 A DE 102007010882A DE 102007010882 A DE102007010882 A DE 102007010882A DE 102007010882 B4 DE102007010882 B4 DE 102007010882B4
Authority
DE
Germany
Prior art keywords
solder
substrate
semiconductor chip
surface area
metal coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102007010882A
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German (de)
English (en)
Other versions
DE102007010882A1 (de
Inventor
Volker Gabler
Thomas Dr. Licht
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE102007010882A priority Critical patent/DE102007010882B4/de
Priority to JP2008050828A priority patent/JP2008277757A/ja
Publication of DE102007010882A1 publication Critical patent/DE102007010882A1/de
Application granted granted Critical
Publication of DE102007010882B4 publication Critical patent/DE102007010882B4/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/417—Bonding materials between chips and die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07178—Means for aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07332—Compression bonding, e.g. thermocompression bonding
    • H10W72/07333—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07336—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

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  • Die Bonding (AREA)
DE102007010882A 2007-03-06 2007-03-06 Verfahren zur Herstellung einer Lötverbindung zwischen einem Halbleiterchip und einem Substrat Expired - Fee Related DE102007010882B4 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE102007010882A DE102007010882B4 (de) 2007-03-06 2007-03-06 Verfahren zur Herstellung einer Lötverbindung zwischen einem Halbleiterchip und einem Substrat
JP2008050828A JP2008277757A (ja) 2007-03-06 2008-02-29 半導体チップと基板との間の半田接続部およびその製造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102007010882A DE102007010882B4 (de) 2007-03-06 2007-03-06 Verfahren zur Herstellung einer Lötverbindung zwischen einem Halbleiterchip und einem Substrat

Publications (2)

Publication Number Publication Date
DE102007010882A1 DE102007010882A1 (de) 2008-09-25
DE102007010882B4 true DE102007010882B4 (de) 2009-01-29

Family

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Family Applications (1)

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DE102007010882A Expired - Fee Related DE102007010882B4 (de) 2007-03-06 2007-03-06 Verfahren zur Herstellung einer Lötverbindung zwischen einem Halbleiterchip und einem Substrat

Country Status (2)

Country Link
JP (1) JP2008277757A (enExample)
DE (1) DE102007010882B4 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI403004B (en) * 2009-09-04 2013-07-21 Led package structure for increasing heat-dissipating effect and light-emitting efficiency and method for making the same
CN101920405B (zh) * 2010-08-23 2013-07-31 中国电力科学研究院 一种镀锌钢接地网用锡铅基复合钎料及其制备方法
CN115609102B (zh) * 2022-09-26 2025-06-03 西安空间无线电技术研究所 一种芯片热沉组件低空洞率焊接方法
CN115945754A (zh) * 2022-12-28 2023-04-11 哈尔滨工业大学重庆研究院 一种降低铅锡银焊接元器件空洞率的焊接工艺
CN119506864A (zh) * 2024-11-12 2025-02-25 南京航空航天大学 一种用于水下激光熔覆的自动定位装置与方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291314A (ja) * 1992-04-10 1993-11-05 Fujitsu General Ltd ベアチップの半田付方法
DE4235908A1 (de) * 1992-10-23 1994-04-28 Telefunken Microelectron Verfahren zum Verlöten eines Halbleiterkörpers mit einem Trägerelement
EP1350588A2 (en) * 2002-03-29 2003-10-08 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device
DE102005001713A1 (de) * 2004-01-20 2005-08-11 Denso Corp., Kariya Verfahren zum Herstellen eines Verbindungsaufbaus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368571A (en) * 1976-11-30 1978-06-19 Nec Home Electronics Ltd Production of semiconductor device
JPS53109477A (en) * 1977-03-07 1978-09-25 Toshiba Corp Mounting method of semiconductor element
JPH0797701B2 (ja) * 1990-11-05 1995-10-18 松下電器産業株式会社 リフロー半田付け方法
JP3753524B2 (ja) * 1997-11-20 2006-03-08 株式会社日立製作所 電子部品の製造方法
JP2006054227A (ja) * 2004-08-10 2006-02-23 Hitachi Ltd 半導体パワーモジュール及び半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291314A (ja) * 1992-04-10 1993-11-05 Fujitsu General Ltd ベアチップの半田付方法
DE4235908A1 (de) * 1992-10-23 1994-04-28 Telefunken Microelectron Verfahren zum Verlöten eines Halbleiterkörpers mit einem Trägerelement
EP1350588A2 (en) * 2002-03-29 2003-10-08 Fuji Electric Co., Ltd. Method of manufacturing semiconductor device
DE102005001713A1 (de) * 2004-01-20 2005-08-11 Denso Corp., Kariya Verfahren zum Herstellen eines Verbindungsaufbaus

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Energiesparendes Lötverfahren für lunkerfreie Verbindung: Im Vakuum löten. In: Elektronik Produktion und Prüftechnik (EPP), ISSN 0943-0962, Juni 2001, S. 24; *
In Vakuumlötanlagen: Oxidations- und lunkerfreies Löten. In: Elektronik Produktion und Prüftechnik ( EPP), ISSN 0943-0962, Nov. 1994, S. 38-40; Energie sparendes Lötverfahren für lunkerfreie Verbindung: Im Vakuum löten. In: Elektronik Produktion und Pr üftechnik (EPP), ISSN 0943-0962, Juni 2001, S. 24
In Vakuumlötanlagen: Oxidations- und lunkerfreies Löten. In: Elektronik Produktion und Prüftechnik (EPP), ISSN 0943-0962, Nov. 1994, S. 38-40; *

Also Published As

Publication number Publication date
JP2008277757A (ja) 2008-11-13
DE102007010882A1 (de) 2008-09-25

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8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee