CN207587728U - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN207587728U
CN207587728U CN201721440133.6U CN201721440133U CN207587728U CN 207587728 U CN207587728 U CN 207587728U CN 201721440133 U CN201721440133 U CN 201721440133U CN 207587728 U CN207587728 U CN 207587728U
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China
Prior art keywords
semiconductor element
lead frame
substrate
coupled
encapsulation
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CN201721440133.6U
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English (en)
Inventor
林承园
钟马尅
孙焌瑞
全五燮
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QUICK KOREA SEMICONDUCTOR CO Ltd
Fairchild Korea Semiconductor Ltd
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QUICK KOREA SEMICONDUCTOR CO Ltd
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Abstract

在一个总的方面，一种半导体装置，可以包括半导体管芯、衬底和耦合到衬底的引线框。所述装置可以包括耦合到所述半导体管芯的导电夹。所述引线框可以布置在所述半导体管芯和所述衬底之间，并且所述半导体管芯可以布置在所述导电夹和所述引线框之间。

Description

半导体装置
相关申请
本申请主张对2016年11月1日提交的美国临时专利申请No.62415939的优先权和权益，其全部内容通过引用并入本文。
技术领域
本说明书涉及半导体装置。
背景技术
随着电子行业向更小的尺寸，更高的效率和更低的成本迈进，集成技术在制造更小、更智能、更高效的产品方面，在包括电源管理领域的许多领域都有很大的需求。最高性能的器件(如功率器件)通常是分散制造的，而不是集成在集成电路(integrated circuit，IC)工艺中。生产这种分立器件的成本可以是使用这种复杂工艺生产的器件的成本的一部分，因为在分立器件中使用的掩膜层通常是在更复杂的IC工艺中使用的掩膜层的数量的一部分(例如一半、三分之一)。许多已知的方法使用例如引线框封装和铜夹来实现集成，但是这种封装的缺点是成本较高，散热性能差，电感更高，尺寸更大，并且通常集成度也更低。因此，存在用于系统，方法和设备的需求，以解决现有技术的不足，并提供其他新的和创新的功能。
实用新型内容
在一个总的方面，一种半导体装置，可以包括半导体管芯、衬底和耦合到衬底的引线框。所述装置可以包括耦合到所述半导体管芯的导电夹。所述引线框可以布置在所述半导体管芯和所述衬底之间，并且所述半导体管芯可以布置在所述导电夹和所述引线框之间。
附图说明
图1A至1H是包含在一个封装内的组件的示意图。
图2A到2J是包含在一个封装内的额外组件的示意图。
图3A到3C示出了一个封装内组件的各种视图。
图3D和3E示出了图3A至3C中参考的封装的各种视图。
图4A和4B示出了在图1A至1E中示出的封装的组件的封装的各种视图。
图5A和5B示出的封装的组件的各种视图是在图1A至1E中示出的封装的组件的变型。
图5C和5D示出了图5A和5B中参考的封装的组件。
图6A和6B示出了在图2A至2J中示出的封装的组件的封装的各种视图。
图7是制造包括半导体管芯的封装的方法的示意图。
具体实施方式
本实用新型描述的封装包括衬底(例如直接键合金属(例如铜)衬底)，半导体管芯，引线框(例如扩展引线框)和夹子的各种垂直组合(或堆叠)。这些垂直组合可以导致多管芯模块(multi-chip module，MCM)封装，其不仅具有相对较低的电阻，而且具有高电流能力。在一些实施方案中，半导体管芯可以耦合到引线框的顶部和底部。在一些实施方案中，可以使用夹子(例如，单体夹)来实现相对较低的电阻和/或电感。
图1A是包含在一个封装内的组件100的平面(或俯视)图。所述封装的组件100包括若干半导体管芯10A，10B，10C，12A，12B和12C(可以被称作管芯)，引线框110(例如，冲压引线框110)，和衬底120(其可以是定向键合金属衬底(例如，定向键合铜(directed bondedcopper，DBC)衬底))。在该实施方案中，所述衬底120(用虚线显示，以使图案更容易查看)布置在所述引线框110的下方。换言之，所述引线框110布置在所述衬底120上。
所述衬底120可以是(或可以包括)直接键合铜衬底，其可以包括包含电介质(例如，如图1B所示的电介质122)的堆叠，所述电介质布置在第一金属层(例如，顶部金属层，如图1B所示的金属层121)和第二金属层(例如，底部金属层，如图1B所示的金属层123)之间。在一些实施方案中，当在最终模块形式时(例如，如图4A和4B中所示的封装400)，所述封装的所述组件100可以被称为MCM或者也可以被称为半导体管芯封装。
在一些实施方案中，所述半导体管芯10A至10C中的每个都可以是相对的高压(high-voltage，HV)器件(例如，高侧器件)，所述半导体管芯12A至12C中的每个都可以是相对的低压(low-voltage，LV)的器件(例如，低侧器件)。在该实施方案中，所述高侧器件(半导体管芯10A至10C)在所述封装的所述组件100的AA1侧，并且低侧器件(半导体管芯12A至12C)在所述封装的所述组件100的AA2侧。
在所述封装的所述组件100的AA1侧上的所述引线框110的一部分可以是所述引线框110的信号侧(或信号端)。在所述封装的所述组件100的AA2侧上的所述引线框110的一部分可以是所述引线框110的电源侧(或电源端)。引线框110可以被称为扩展引线框，因为所述引线框110从(耦合到引线框110的电源侧的)引线框110的信号侧延伸至引线框110的电源侧。在该实施方案中，所述高压器件被布置在(和/或耦合至)引线框110的信号侧并且低压器件被布置在(和/或耦合至)引线框110的电源侧。
引线框110从成型件140延伸出的一部分可以被称作引线。所述引线140-AA1延伸自位于所述组件100的AA1侧的所述成型件140，并且所述引线140-AA2延伸自位于所述组件100的AA2侧的所述成型件140。如图1A所示，键合线可以用于栅极连接。
图1B是图1A沿虚线A1的横截面视图的示意图。在该图中，顶部方向朝向页面的顶部，底部方向朝向页面的底部。垂直方向沿分别通过半导体管芯10A和半导体管芯12A的虚线A2和A3(在顶部和底部之间)延伸。所述封装的组件100包括成型件140(例如，成型层)。
如图1B所示，所述半导体管芯10A可以布置在所述引线框110和所述衬底120之间。因此，所述半导体管芯10A被包含在垂直堆叠中，其(从顶部到底部)包括所述引线框110，所述半导体管芯10A和所述衬底120。所述半导体管芯10A被布置在(和耦合至)所述引线框110的至少一部分和所述衬底120之间。具体的，半导体管芯10A被布置在(和耦合至)所述引线框110的至少一部分和所述衬底120的所述金属层121之间。
所述半导体管芯的源极(source，S)和/或栅极(gate，G)可以被耦合至所述引线框110的底部表面。半导体管芯10A的漏极(D)可以被耦合到所述衬底120的顶部表面。具体的，所述半导体管芯10A的漏极(D)可以被耦合至所述衬底120的所述金属层121的顶部表面。
在一些实施方案中，所述半导体管芯10A可以被翻转(朝向不同的方向)以使半导体管芯10A的源极和/或栅极可以耦合到金属层121的顶部表面。在这样的实施方案中，所述半导体管芯10A可以被翻转以使半导体管芯10A的漏极可以被耦合至所述引线框110的所述底部表面。
如图1B所示，所述引线框110可以布置在所述半导体管芯12A和所述衬底120之间。所述半导体管芯12A可以被布置在所述夹子130(例如，导电夹)和所述引线框110之间。所述半导体管芯12A可以耦合至所述夹子130。因此，所述半导体管芯12A被包含在所述的垂直堆叠中，该垂直堆叠(从顶部到底部)包含有夹子130、所述半导体管芯12A、所述引线框110和所述衬底120。所述半导体管芯12A被布置在(和耦合至)所述夹子130和所述引线框110的至少一部分之间。所述引线框110被布置在(和耦合至)所述半导体管芯12A的底部表面和所述衬底120的所述金属层121之间。
所述夹子130(所述夹子130的第一部分)可以被耦合至(例如，直接耦合至)所述半导体管芯12A的源极(S)和/或栅极(G)。所述夹子130(所述夹子130的第二部分)可以通过所述引线框110内的开口112(同样可以称为窗口)被耦合至所述衬底120的金属层121的顶部表面。因此，所述半导体管芯12A的源极(S)和/或栅极(G)可以通过夹子130被电耦合至所述衬底120的所述金属层121的顶部表面。所述夹子130可以被耦合至在所述引线框110电源侧上的引线框110的管芯连接焊盘(die attach pad，DAP)。
半导体管芯12A的漏极(drain，D)可以被耦合到所述引线框110的顶部表面。具体的，所述半导体管芯12A的所述漏极(D)可以被耦合至所述衬底120的所述金属层121的顶部表面。因此，所述半导体管芯12A的所述漏极(D)可以通过引线框110被电耦合至所述衬底120的所述金属层121的顶部表面。此外，所述半导体管芯12A的所述漏极(D)可以通过所述引线框110被电耦合至所述半导体管芯10A的所述源极和/或栅极。
在一些实施方案中，所述半导体管芯12A可以被翻转以使所述半导体管芯12A的所述源极和/或栅极可以耦合到所述引线框110。在这样的实施方案中，所述半导体管芯12A可以被翻转以使所述半导体管芯12A的漏极可以被耦合至所述夹子130。
如图1B所示，所述引线框110可以有限定了凹部(在所述弯曲部分的凹陷部分内)的多个弯曲部分113、114和115。这些凹部可以在所述引线框110和所述衬底120之间限定一个或多个空腔。在该实施方案中，所述弯曲部分113，114和115中的每个都可以限定具有朝向所述衬底120的凹陷表面(或部分)的凹陷形状(或凹部)。在一些实施方案中，所述弯曲部分113，114和115可以被称为弯曲部分或凹陷部分。如图1B所示，所述弯曲部分113，114，115可以有多于一处的弯曲(例如，多于一个的拐点)。
在该实施方案中，所述弯曲部分113包括所述开口112的至少一部分。因此，所述夹子130可以有至少一部分布置在所述引线框110的所述弯曲部分113内部的所述开口112内。在该实施方案中，所述开口112被布置在(例如居中布置)所述弯曲部分113的一侧。在一些实施方案中，所述开口112可以被布置在所述弯曲部分113的中部。在该实施方案中，当从侧面看时，所述开口112是弯曲的(例如，具有拐点或者是弯的)。在一些实施中，当从顶部看时(例如，当从图1A看时)所述开口112的形状或轮廓可以是正方形的或矩形的。
如图1B所示，所述半导体管芯12A被布置在所述引线框110的顶部，位于弯曲部分113和弯曲部分114之间。因此，所述弯曲部分113，114(其拥有朝下的凹陷表面)在它们之间定义了所述引线框110的凹陷部分(凹陷表面朝上)，其上布置有半导体管芯12A，以及定义了接触所述衬底120的凸出部分(凸出表面朝下)(例如，所述衬底120的所述金属层121)。
所述半导体管芯10A可以布置在弯曲部分114和弯曲部分115之间。因此，所述弯曲部分114，115(其拥有朝下的凹陷表面)在它们之间定义了所述引线框110的与所述半导体管芯10A耦合的凸出部分(突出表面朝下)。
所述引线框110的弯曲部分113的一部分(在所述弯曲部分113的左侧)不接触(例如，通过间隙隔开)所述衬底120(例如，所述衬底120的金属层121)。具体的，所述成型件140的一部分将所述弯曲部分113的一部分与所述衬底120隔开。
所述引线框110的弯曲部分115的一部分(在所述弯曲部分115的右侧)不接触(例如，通过间隙隔开)所述衬底120(例如，所述衬底120的金属层121)。具体的，所述成型件140的一部分将所述弯曲部分115的一部分与所述衬底120隔开。
在一些实施方案中，所述衬底120的至少一部分(例如，底部部分，所述金属层123的底部部分)可以通过成型件140暴露。在一些实施方案中，所述成型件140可以完全封装衬底120以使所述衬底120的一部分不通过成型件140暴露。
如图1B所示，在一些实施方案中，所述开口112的侧壁的至少一部分可以与所述衬底120的所述金属层121接触。在一些实施方案中，所述开口112的侧壁的至少一部分可以布置在所述衬底120的金属层上方或者与其隔离开。
如图1B所示，所述引线框110沿平面P1对齐。所述引线110-AA1、110-AA2沿平面P1对齐。
如图1B所示，所述半导体管芯12A沿平面P1对齐(例如平行)，但是布置在所述平面P1的上方。所述半导体管芯10A沿平面P1对齐(例如平行)，但是布置在所述平面P1的下方。因此，所述半导体管芯12A(位于AA2侧)被布置在所述引线框110的一侧(例如顶侧)，并且所述半导体管芯10A(位于AA1侧)被布置在所述引线框110的对侧(例如底侧)。
图1C是所述夹子130、所述衬底120和半导体管芯12A-12C的示意图。图1C中的图包括了如图1A所示的组件的一个子集。如图1C所示，所述衬底120的所述金属层121可以被图案化。如图1C所示，所述夹子130可以被图案化。
如图1C所示，所述夹子130有多个凸起130-1，130-2(例如，触点，插脚(prong)(例如两个插脚))耦合至所述半导体管芯12A。在一些实施方案中，所述夹子130可以具有更多或更少的凸起。
图1D是所述夹子130，所述衬底120以及所述半导体管芯12A沿图1C中(和图1A中)所示的A1线切割的侧视图。如图1D所示，所述夹子130有多处弯曲。具体的，所述夹子130定义了具有朝向所述衬底120的凹陷部分的凹形。
如图1D所示，所述夹子130具有耦合至所述半导体管芯12A的第一端或端部131。所述端部131包括凸起130-1和130-2。所述夹子130具有耦合至所述衬底120的第二端或端部132。
图1E是所述引线框110的一部分和所述半导体管芯12A-12C的示意图。在图1D中的图包括了如图1A所示的组件的一个子集。
图1F是所述引线框110的一部分沿图1E(和图1A)所示的线A1切割的侧面横截面图的示意图。
如图1F所示，距离N(例如，厚度)是所述引线框110位于弯曲部分114和115之间的一部分和所述引线框110的底部之间(用虚线示出)。所述距离N可以近似等于所述半导体管芯10A的厚度(较少的导电组件(例如焊接)以将所述半导体管芯10A耦合至引线框110和衬底120)。
图1G是图1A中所示的所述封装的所述组件100的一部分的视图。图1H是图1B中所示的封装的组件100的一部分的视图。图1G和图1H大体上示出了被封装在所述成型件140中的组件100的一部分。
在一些实施方案中，所述成型件140可以包括，或者可以是成型化合物。因此，所述成型件140可以包括成型材料中的多于一种材料(例如，塑料，树脂，环氧树脂，酚醛固化剂，二氧化硅材料，颜料等)。
所述半导体管芯(例如半导体管芯10A至10C，半导体管芯12A至12C，半导体管芯11)可以是或者可以包括各种器件，例如双极结型晶体管(bipolar junction transistor，BJT)，二极管，绝缘栅双极晶体管(an insulated gate bipolar transistor，IGBT)，超导场效应晶体管(superjunction field effect transistor，FET)，金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor，MOSFET)器件，碳化硅(SiC)器件(例如SiCk BJT)，或者其他的晶体管器件。在一些实施方案中，一个或多个半导体管芯可以是，或者可以包括，诸如滤波电路、控制器电路、驱动器电路、通信电路(例如，接收机和/或发射机)等的电路。在一些实施方案中，半导体管芯中的一个或多个可以是，或者包括，专用逻辑电路、组合逻辑、现场可编程门阵列(field programmable gate array，FPGA)、专用集成电路(application-specific integrated circuit，ASIC)等。在一些实施方案中，所述封装(和/或半导体管芯中的一个或多个)可以被用作许多不同种类的系统，例如功率控制系统、射频(radio frequency，RF)系统、控制器系统、计算系统、数字和/或模拟系统等。所述半导体管芯中的一个或多个可以包括，例如在其中实现的高压(high-voltage，HV)(或高侧)或低压(low-voltage，LV)(或低侧)晶体管，诸如场效应晶体管(例如，垂直FET，横向FET)。在一些实施方案中，所述封装可以包括多于两个半导体管芯或者少于两个半导体管芯。
在如图1A至1H所示的实施方案中，所述衬底120可以用作一种平台，通过该平台可以建立用于多种半导体器件(半导体管芯)的连接。具体的，例如，所述电子连接可以通过例如可以耦合至所述衬底120的所述金属层121和/或所述金属层123提供。在一些实施方案中，所述衬底120(或与之耦合的导电组件(例如金属层121))可以被焊接在例如所述引线框110的部分上，以与所述封装内部的至少一部分组件(例如半导体管芯)建立电连接。在一些实施方案中，所述金属层121和/或所述金属层123可以包括一条或多条轨迹线，所述轨迹线可以为几微米宽和/或厚(例如，10微米，30微米，40微米)或者更宽和/或更厚(例如，大于40微米，100微米)。
所述衬底120可以包括诸如一个或多个导体(例如铝导体(或其合金)，铜导体(或其合金))的各种金属层(例如，金属层121，金属层123)和/或一种或多种电介质(例如，陶瓷材料，预成型材料，有机材料)。在一些实施方案中，所述衬底120可以包括导体和/或电介质的一个或多个层(例如堆叠层)。例如，在一些实施方案中，所述衬底120可以包括布置在定向键合铜(DBC)中的第一导体和第二导体之间的电介质。作为另一种例子，在一些实施例中，所述衬底120可以包括单个导体和单个电介质。
图2A是包含在一个封装内的组件200的平面(或俯视)图。图2A中所示的所述封装的组件200图1A至图1G中所示的所述封装的组件100的变形。因此，即使没有明确的标记或描述，所述封装的组件100的几乎所有特征都被并入所述封装的所述组件200中。所述封装的组件200包括若干半导体管芯20A，20B，20C，22A，22B和22C(可以被称作管芯)，引线框210和衬底220(其可以是定向键合金属衬底(例如，定向键合铜(DBC)衬底))。所述封装的组件200的引线框210在BB1侧有信号侧，并且在BB2侧有电源侧。所述引线框210包括引线210-BB1、210-BB2。
在该实施方案中，所述半导体管芯(例如，半导体管芯20A-20C和22A-22C)被布置在所述引线框210的同侧。因此，夹子被从该实施方案中排除，该实施方案可以被称为无夹实施方案。
图2B和2C是图2A分别沿虚线B1和B2的横截面示意图。垂直方向沿分别穿过半导体管芯22A和半导体管芯20C的虚线B3和B4延伸。所述封装的组件200包括成型件240。在这些图中，顶部方向朝向页面的顶部，底部方向朝向页面的底部。
如图2B所示，所述半导体管芯22A可以布置在所述引线框210和所述衬底220之间。因此，所述半导体管芯22A被包含在垂直堆叠中，其(从顶部到底部)包括所述引线框210、所述半导体管芯22A和所述衬底220。
所述半导体管芯22A的源极(S)和/或栅极(G)可以被耦合至所述引线框210的底部表面。半导体管芯22A的漏极(D)可以被耦合到所述衬底220的顶部表面。具体的，所述半导体管芯22A的所述漏极(D)可以被耦合至所述衬底220的所述金属层221的顶部表面。
如图2C所示，所述半导体管芯20C可以布置在所述引线框210和所述衬底220之间。因此，所述半导体管芯20C被包含在垂直堆叠中，其(从顶部到底部)包括所述引线框210、所述半导体管芯20C和所述衬底220。
所述半导体管芯20C的源极(S)和/或栅极(G)可以被耦合至所述引线框210的底部表面。所述半导体管芯20C的漏极(D)可以被耦合到所述衬底220的顶部表面。具体的，所述半导体管芯22A的所述漏极(D)可以被耦合至所述衬底220的所述金属层221的顶部表面。
如图2B和2C所示，引线框210沿平面P2对齐，并且所述引线210-BB1、210-BB2沿平面P2对齐。所述半导体管芯22A和20C沿平面P2对齐(例如与平面P2平行)，但是布置在所述平面P2的下方。因此，半导体管芯20C和22A(二者分别位于BB1侧和BB2侧)都布置在所述引线框210的一侧(例如底侧)。
在本实施例中，所述引线框210的耦合至半导体管芯20A-20C和/或22A-22C中每一个的部分的形状有至少一个凸起(例如，多个凸起(例如，叉形))。例如，耦合至半导体管芯22C的部分214的形状有多个凸起。在一些实施方案中，所述引线框210的耦合至半导体管芯中每一个的一个或多个部分可以拥有不同的形状。如图所示，凸起(其可以用作触点)可以具有不同的长度。所述引线框210的耦合至半导体管芯20A-20C中的至少一些的部分中的至少一些是平行条。
如图2A所示，所述引线框210包括可以在成型件240被包括在封装的组件200中之后被移除(例如，切断，隔断)的部分213。所述部分213可以在所述成型件被包括在所述封装的组件200中之后被布置在所述成型件240的外面(例如，暴露在外侧)。因此，所述引线框210的所述部分214可以与所述引线框210的其余部分去耦合(例如，与引线框210的电源侧去耦合)。在一些实施方案中，所述引线框210的所述部分214可以与所述引线框210的其余部分电隔离(例如，绝缘)。在一些实施方案中，所述引线框210的所述部分213可以在所述成型件240被包括在所述封装的组件200中之前被移除。
在与所述引线框210的剩余部分分隔开之后，所述部分214可以用作从所述半导体管芯22C到所述衬底220的夹子(例如，单体夹)。因此，所述部分214可以作为扩展引线框夹子。所述引线框210可以包括与部分213和部分214类似的部分。
在一些实施方案中，所述半导体管芯20A至20C和/或半导体管芯22A至22C中的任意一个都可以被翻转以使所述半导体管芯的源极和/或栅极可以被耦合至所述金属层221的顶部表面。在这样的实施方案中，所述半导体管芯可以被翻转以使所述半导体管芯的漏极可以被耦合至所述引线框210的所述底部表面。
如图2B所示，所述引线框210定具有弯曲部分216，其具有朝向所述衬底220的凹面。所述弯曲部分216的第一端被耦合至所述半导体管芯22A，并且所述弯曲部分216的第二端被耦合至所述衬底220(例如，所述衬底220的金属层221)。
如图2C所示，所述半导体管芯10A可以布置在弯曲部分217和弯曲部分218之间。因此，所述弯曲部分217、218定义了所述引线框110的与所述半导体管芯20A耦合的突出部分(凸面朝下)。
图2D是如图2A所示的衬底220的俯视图示意图。在图2D中的图包括了如图2A所示的组件200的子集。如图2D所示，所述衬底220的金属层221可以被图案化。
图2E是如图2A所示的引线框210的一部分的示意图。图2F和2G是对应于图2B和2C的所述引线框210的侧面横截面视图的示意图。这些图中包括了如图2A中所示的组件200的一个子集。如图2F所示的引线框210的部分(如图2E中所示)沿线B6切开，并且如图2G所示的引线框210的部分沿线B7切开(如图2E中所示)。
图2H是图2A中所示的封装200的组件200的一部分的示意图。图2I和2J是与图2B和2C对应的封装的组件200的侧面横截面的示意图。这些图中包括了如图2A中所示的组件200的子集。如图2I所示的引线框210的部分(如图2H中所示)沿线B6切开，并且如图2J所示的引线框210的部分沿线B7切开(如图2H中所示)。
如图2H所示，所述引线框210可以具有多个凹部：216-1，217-1，218-1和219-1。这些凹部可以限定所述引线框210和所述衬底220之中的一个或多个空腔。
因为所述凹部216-1的存在，所述引线框210的一部分不接触(例如，通过间隙隔开)所述衬底220(例如，所述衬底220的金属层221)。具体的，所述成型件240的一部分将所述引线框210的与凹部216-1相关联的一部分与所述衬底220隔开。
因为所述凹部218-1的存在，所述引线框210的一部分不接触(例如，通过间隙隔开)所述衬底220(例如，所述衬底220的金属层221)。具体的，所述成型件240的一部分将所述引线框210的与凹部218-1相关联的一部分与所述衬底220隔开。
如图2I和2J所示，所述凹部216-1的轮廓(例如，形状)与所述凹部219-1的轮廓(例如，形状)不同。所述引线框210在凹部219-1的两侧都与所述衬底220接触，并且在凹部216-1的两侧都不与所述衬底220接触。所述凹部216-1位于所述凹部219-1(从图2H的平面图的角度来看)的侧面(例如，在左侧)。
图3A至3C示出了封装301的组件300的各种视图。这该实施方案中，所述封装301的组件300包括在所述引线框310的部分和所述半导体管芯30之间的焊线350。图3D和3E示出了在最终模块形式下的封装301的各种视图。
图4A和4B示出了在图1A至1E中示出的封装的组件100在最终模块形式下的封装400的各种视图。
图5A和5B示出的封装501的组件500的各种视图是在图1A至1E中示出的封装的组件100的变型。图5C和5D示出了在最终模块形式下的所述封装501的所述组件500的各种视图。与一些图中示出的实施例不同，所述封装500包括6个MOSFET半导体管芯而不包括其他半导体管芯(例如图1A中所示的半导体管芯11)。
图6A和6B示出了在图2A至2J中示出的封装的所述组件200在最终模块形式下的封装600的各种视图。如图6A所示，所述部分213已经被移除以使所述部分214和所述引线框210之间有缝隙。在移除掉所述部分213之后，保留在所述成型件240之内的引线框210的部分(例如，扩展引线框夹子)的侧面横截面视图如图2J中所示。
图7是制造包括半导体管芯的封装的方法的示意图。如图7所示，所述方法包括：在框S710，将半导体管芯耦合到衬底(例如DBC)。在框S720，将引线框耦合到半导体管芯。在框S730，将所述引线框的至少一部分、所述半导体管芯和所述衬底封装在成型件中。在框S740，通过去除所述引线框的布置在所述成型件外部的部分在成型件内形成夹。在一些实施方案中，因为所述夹子是从所述引线框形成的，所以所述夹子可以称为扩展引线框夹子。所述引线框的所述部分被移除以使所述引线框的耦合在所述半导体管芯和所述衬底之间的部分和所述引线框的剩余部分之间有缝隙。如上文所述，图2J示出了在移除掉所述部分213之后，保留在所述成型件240之内的所述引线框210的所述部分(例如，扩展引线框夹)的横截面侧面的视图。
如图3D、3E、4A、4B、5C、5D、6A和6B所示，所述引线框的引线相对于所述引线框的布置在成型层内部的部分是弯的。在一些实施方案中，所述引线中的一条或多条与所述引线框的布置在成型层中的部分垂直对齐(例如，基本垂直。
在一个总的方面，一种装置，可以包括半导体管芯、衬底和耦合到所述衬底的引线框。所述装置可以包括耦合到所述半导体管芯的导电夹。所述引线框可以布置在所述半导体管芯和所述衬底之间，并且所述半导体管芯可以布置在所述导电夹和所述引线框之间。
在一些实施方案中，所述装置可以包括封装所述半导体管芯的成型层。在一些实施方案中，所述装置可以包括封装所述半导体管芯的成型层，以及所述引线框可以具有从成型层延伸出的引线部分。
在一些实施方案中，所述装置包括垂直堆叠，其从顶部到底部包含导电夹、半导体管芯、引线框和衬底。在一些实施方案中，所述半导体管芯是第一半导体管芯。所述装置还可以包括第二半导体管芯，并且所述第二半导体管芯可以布置在所述引线框和所述衬底之间。在一些实施方案中，所述半导体管芯是耦合至所述引线框顶侧的第一半导体管芯。所述装置可以包括耦合至所述引线框底侧的第二半导体管芯。
在一些实施方案中，所述导电夹就有耦合至所述半导体管芯的第一端部分，并且所述导电夹具有耦合至所述衬底的第二端部分。在一些实施方案中，所述引线框包括开口，并且所述导电夹的一部分布置在所述开口内。在一些实施方案中，所述引线框包括开口，所述导电夹具有耦合至所述半导体管芯的第一端部分，并且所述导电夹具有通过所述开口耦合至所述衬底的第二端部分。
在一些实施方案中，所述衬底包括布置在第一金属层和第二金属层之间的介电层。在一些实施方案中，第一金属层是铜金属层。
在一个总的方面，所述装置可以包括引线框、耦合至所述引线框顶侧的第一半导体管芯以及耦合至所述引线框底侧第二半导体管芯。所述装置可以包括耦合至所述引线框底侧的衬底以及耦合至所述第一半导体管芯的顶侧的导电夹。
在一些实施方案中，所述第一半导体管芯布置在所述引线框和所述衬底之间。在一些实施方案中，所述导电夹耦合在所述第一半导体管芯的源极和栅极之间。所述第一半导体管芯具有耦合至所述引线框的漏极，以及耦合至所述衬底的漏极。在一些实施方案中，所述第二半导体管芯具有耦合至所述引线框底侧的源极和栅极，以及耦合至所述衬底的顶侧的漏极。在一些实施方案中，所述第一半导体管芯包括低电压器件，以及所述第二半导体管芯具有耦合至所述引线框顶侧的漏极。
在另一个总的方面，一种装置，包括第一半导体管芯、第二半导体管芯和衬底。所述装置可以包括耦合至所述衬底的引线框，以及耦合至所述第一半导体管芯的导电夹。所述引线框可以布置在所述第一半导体管芯和所述衬底之间，并且所述第二半导体管芯可以布置在所述引线框和所述衬底之间。
在一些实施方案中，所述装置包括第一垂直堆叠，其从顶部到底部包含所述导电夹、所述第一半导体管芯、所述引线框的第一部分和所述衬底。所述装置包括第二垂直堆叠，其从顶部到底部包含所述引线框的第二部分、所述第二半导体管芯和所述衬底。
在一些实施方案中，所述第一半导体管芯耦合至所述引线框的顶侧，并且所述第二半导体管芯耦合至所述引线框的底侧。在一些实施方案中，所述衬底包括布置在第一金属层和第二金属层之间的介电层。
还将理解，当诸如晶体管或电阻器的元件，被称为与另一个元件连接，电连接，耦合，或电耦合时，其可以直接与所述另一个元件连接或耦合，或者可以在所述连接或耦合中存在一个或多个中间元件。相比之下，当元件被称为直接连接或直接连接到或直接耦合至另一元件或层时，不存在中间元件或层。尽管在整个说明书中术语“直接”、“直接连接”或“直接耦合”可能没有被使用，但是在图中被示出为“直接”、“直接连接”或“直接耦合”的元件可以这样称呼。本申请的权利要求书(如果包含的话)可以被修改以描述本说明书中描述的或附图中所示的示例性关系。
如本说明书中所使用的，除非上下文明确指出的特定情况，否则单数形式可以包括复数形式。空间相对术语(例如，之上，上方，上面，之下，下方，下面，以及低于等)旨在包括除了图中所示的取向之外的装置的使用或操作中的不同取向。在一些实施方案中，相对术语“上方”和“下方”可以分别包含垂直上方和垂直下方。在一些实施方案中，术语“相邻”可以包括横向相邻或水平相邻。
本文描述的各种技术的实施方案可以在数字电路中实现(例如，包括在数字电路中)，或在计算机硬件、固件、软件或它们的组合中实现。方法的一部分以及装置也可以通过专用逻辑电路实现，例如FPGA(现场可编程门阵列)或ASIC(专用集成电路)。
实施方案可以通过包含以下器件的计算机系统实施：工业电动机驱动器、太阳能逆变器、镇流器、通用半桥拓扑，辅助和/或牵引电动机反相器驱动器，开关模式电源、板载充电器、不间断电源(uninterruptible power supply，UPS)、后端组件(例如，作为数据服务器)，或者包括中间件组件(例如应用服务器)，或者包括前端组件(例如具有用户图形界面或web浏览器的客户端计算机，用户可以通过该用户图形界面或web浏览器与实施方案进行交互)，或者这种后端、中间件或前端组件的任意组合。组件可以通过数字数据通信的任何形式或介质互连，例如通信网络。通信网络的示例包括局域网(local area network，LAN)和诸如因特网的广域网(wide area network，WAN)。
一些实施方案可以通过使用各种半导体处理和/或封装技术来实现。一些实施方案可以通过使用与半导体衬底(包括但不限于，例如硅(Si)，砷化镓(GaAs)，氮化镓(GaN)，等等)相关联的各种类型的半导体处理技术来实现。
尽管所描述的实施方案的某些特征已经在本文中做出了描述，但是现在本领域技术人员将会想到许多修改，替换，改变和等价物。因此，应当理解，所附权利要求旨在涵盖落入实施方案的范围内的所有这样的修改和改变。应当理解，它们仅以示例的方式呈现，而不是限制，并且可以进行形式和细节的各种改变。除了相互排斥的组合之外，本文描述的装置和/或方法的任何部分可以任意组合。本实用新型描述的实施方案可以包括所描述的不同实施方案的功能，组件和/或特征的各种组合和/或子组合。

Claims (11)

1.一种半导体装置，其特征在于，包括：
半导体管芯；
衬底；
耦合到所述衬底的引线框；以及
耦合至所述半导体管芯的导电夹，所述引线框布置在所述半导体管芯和所述衬底之间，所述半导体管芯布置在所述导电夹和所述引线框之间。
2.根据权利要求1所述的半导体装置，还包括：封装所述半导体管芯的成型层。
3.根据权利要求1所述的半导体装置，还包括：封装所述半导体管芯的成型层，所述引线框具有从所述成型层延伸出的引线部分。
4.根据权利要求2所述的半导体装置，其中，所述装置包括垂直堆叠，所述垂直堆叠从顶部到底部包括所述导电夹、所述半导体管芯、所述引线框和所述衬底。
5.根据权利要求1所述的半导体装置，其中，所述半导体管芯是第一半导体管芯，
所述半导体装置还包括：
第二半导体管芯，所述第二半导体管芯被布置在所述引线框和所述衬底之间。
6.根据权利要求1所述的半导体装置，其中，所述半导体管芯是耦合至所述引线框的顶侧的第一半导体管芯，
所述半导体装置还包括：
耦合至所述引线框的底侧的第二半导体管芯。
7.根据权利要求1所述的半导体装置，其中，所述导电夹具有耦合至所述半导体管芯的第一端部分，并且所述导电夹具有耦合至所述衬底的第二端部分。
8.根据权利要求1所述的半导体装置，其中，所述引线框包括开口，所述导电夹的一部分布置在所述开口内。
9.根据权利要求1所述的半导体装置，其中，所述引线框包括开口，所述导电夹具有耦合至所述半导体管芯的第一端部分，并且所述导电夹具有通过所述开口耦合至所述衬底的第二端部分。
10.根据权利要求1所述的半导体装置，其中，所述衬底包括布置在第一金属层和第二金属层之间的介电层。
11.根据权利要求10所述的半导体装置，其中，所述第一金属层是铜金属层。
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