CN109698178B - 半导体装置设备及其形成方法 - Google Patents

半导体装置设备及其形成方法 Download PDF

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Publication number
CN109698178B
CN109698178B CN201811222068.9A CN201811222068A CN109698178B CN 109698178 B CN109698178 B CN 109698178B CN 201811222068 A CN201811222068 A CN 201811222068A CN 109698178 B CN109698178 B CN 109698178B
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die
gate
semiconductor
silicon carbide
semiconductor die
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CN109698178A (zh
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J·泰塞伊雷
M·C·埃斯塔西奥
林承园
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本申请涉及半导体装置设备及其形成方法。在一般方面中，一种半导体装置设备可包含：封装，其包含共同栅极导体；第一碳化硅裸片，其具有裸片栅极导体；及第二碳化硅裸片，其具有裸片栅极导体。所述设备可包含：第一导电路径，其在所述共同栅极导体与所述第一碳化硅裸片的所述裸片栅极导体之间；及第二导电路径，其在所述共同栅极导体与所述第二碳化硅裸片的所述裸片栅极导体之间，其中所述第一导电路径具有大体上等于所述第二导电路径的长度的长度。

Description

半导体装置设备及其形成方法
技术领域
本发明涉及包含半导体装置的封装，例如经封装的半导体装置设备。
背景技术
随着电子器件领域向更小的尺寸、更高的效率和更低的成本发展，在包含功率管理空间的各种空间中制造更小、更智能且更有效的产品非常需要集成技术。最高性能的装置(例如功率装置)通常被离散地制造，而不是集成在集成电路(IC)工艺中。生产此类离散装置的成本可为使用此类复杂工艺生产的装置的一小部分，因为离散装置中使用的掩模层一般是更复杂的IC工艺中使用的掩模层的数量的一小部分(例如，一半、三分之一)。许多已知方法已经使用例如引线框封装和铜夹片来实现集成，但此类封装的缺点是成本更高、热性能较差、电感更高、尺寸更大且集成度通常更低。因此，需要解决本技术的缺点并提供其它新颖且具创造性特征的系统、方法和设备。
发明内容
在一般方面中，一种设备可包含：封装，其包含共同栅极导体；第一半导体裸片，其具有裸片栅极导体；及第二半导体裸片，其具有裸片栅极导体。所述设备可包含：第一导电路径，其在所述共同栅极导体与所述第一半导体裸片的所述裸片栅极导体之间；及第二导电路径，其在所述共同栅极导体与所述第二半导体裸片的所述裸片栅极导体之间，其中所述第一导电路径具有大体上等于所述第二导电路径的长度的长度。
在另一般方面中，一种方法包括：形成形成包含共同栅极导体的第一导电金属层；将多个半导体裸片耦合到所述第一导电金属层的所述共同栅极导体，所述多个半导体裸片包含第一碳化硅裸片和第二碳化硅裸片；及将所述第一导电金属层和所述半导体裸片的至少一部分囊封在绝缘体内，所述第一导电金属层包含所述共同栅极导体与所述第一碳化硅裸片的裸片栅极导体之间的第一导电路径和所述共同栅极导体与所述第二碳化硅裸片的裸片栅极导体之间的第二导电路径，所述第一导电路径具有大体上等于所述第二导电路径的长度的长度。
附图说明
图1A是说明包含安置在封装内的封装的模块的侧部横截面视图的图。
图1B是图1A中展示的模块的仰视图。
图2A到2D是说明内封装的组件的各种平面图的图。
图2E是说明复合堆叠中的图2A到2D中展示的组件的平面图的图。
图3A到3D是说明内封装的变型的组件的各种平面图的图。
图3E是说明复合堆叠中的图3A到3D中展示的组件的平面图的图。
图4A到4L是说明内封装的变型的组件的各种平面图的图。
图5A是说明内封装的组件的平面图的图。
图5B是说明图5A中展示的内封装的组件的变型的平面图的图。
图5C是说明图5A中展示的内封装的组件的变型的平面图的图。
图5D是说明图5B中展示的内封装的组件的变型的平面图的图。
图5E是说明图5B中展示的内封装的组件的变型的平面图的图。
图6到8是说明包含安置在封装内的封装的模块的组件的侧部横截面视图的图。
图9A到9D说明制造本文描述的内封装的至少一部分的方法。
图10A到10D说明图9A到9D中展示的制造方法的变型。
图11说明制造包含在模块内的内封装的方法。
图12是说明可使用本文描述的模块实施的电路配置的图。
图13A到13D是说明模块的各种视图的图。
图14A和14B是说明模块的变型的各种视图的图。
图15A到15G是说明模块的各种视图和组件的图。
图16A到16D是说明结合图15A到15G展示和描述的模块的变型的各种视图的图。
图17A到17E是说明结合图15A到16D展示和描述的模块的变型的各种视图的图。
图18A和18B是说明结合至少图17A到17E描述的模块的立体透视图的图。
图19A到19D是说明制造本文描述的装置的方法的图。
具体实施方式
在一些实施方案中，模块可包含多个半导体裸片(例如，碳化硅(SiC)半导体裸片、绝缘栅极双极晶体管(IGBT)、金属氧化物半导体场效晶体管(MOSFET)裸片)，且模块可经配置使得可大致同时切换包含在模块中的多个半导体裸片。具体来说，半导体裸片的引线框、电连接及/或定向可经配置使得半导体裸片的切换甚至可在相对高频下是稳健的。在一些实施方案中，半导体裸片可为或可包含碳化硅半导体裸片。在一些实施方案中，模块可为双冷模块，其中第一衬底在多个半导体裸片的第一侧上且第二衬底在多个半导体裸片的第二侧上。
本文描述的模块可用于具有高电压(例如，高于600V)、高电流密度(例如，在100A与800A之间(例如，400A))和高切换频率(例如，大于1kHz)的应用中。考虑到碳化硅装置的带隙电压，碳化硅裸片可特别有利于用于高电压应用中。由于电流密度，用于处理电流密度的单个裸片的尺寸可为非常大的。考虑到单个大裸片的高成本和相对低的产率(尤其在碳化硅裸片的情况中)，可能期望使用多个裸片，且在一些情况中是必要的。如上文提及，半导体裸片的引线框、电连接及/或定向可经配置使得碳化硅裸片的切换甚至可在相对高频下是稳健的。
在一些实施方案中，本文描述的模块可为或可包含多芯片共同栅极/源极向下薄型封装。在一些实施方案中，描述的模块可为或可包含能够创建例如灵活且低成本SiC无线功率模块组合件的组装工艺。
本文描述的模块和组装方法(例如，使用个别的裸片及/或间隔件)可不如已知组装方法复杂。与已知组装方法比较，本文描述的模块和组装方法可具有预期的倾斜控制、高产率及/或预期的应力/可靠性。在一些实施方案中，本文描述的模块可与烧结工艺(例如，银烧结工艺)兼容，其中使用烧结材料和工艺(其可包含在接合层中)形成组件之间(例如，引线框与半导体裸片之间)的界面。
模块可被包含于各种应用中，包含例如高功率装置应用(例如，大于600V的高功率应用(尤其在使用碳化硅裸片时)、大于400V的高功率应用(例如，在使用硅裸片时))。在一些实施方案中，模块可被包含于各种应用中，包含例如汽车应用(例如，汽车高功率模块(AHPM)、电动车辆、混合电动车辆)、计算机应用、工业装备、机载充电应用、逆变器应用及/或等等。
图1A是说明包含安置在封装120(例如，外封装)内的封装110(例如，内封装，子模块)的模块100的侧部横截面视图的图。横截面是沿着图1B中展示的线Q1切割。图1B是沿着图1A中展示的方向D1观看的模块的仰视图。出于描述目的，包含在内封装110和外封装120中的元件已经进行简化。虽然说明为包含单个内封装，但是，在一些实施方案中，模块100可包含多个内封装。因此，外封装120可包含超过一个内封装(例如，内封装110)。
如在图1A中展示，内封装110包含半导体裸片10A、10B。半导体裸片10A、10B每一者经耦合到(例如，电耦合、直接耦合、通信耦合到)引线框130。间隔件15A、15B分别耦合到半导体裸片10A、10B。因此，半导体裸片10A、10B中的每一者安置在间隔件15A、15B与引线框130之间。半导体裸片10A、10B沿着相同平面Q4对准。
虽然内封装110被说明和描述为仅包含两个半导体裸片，但是内封装110可包含超过两个半导体裸片(例如，3个半导体裸片、6个半导体裸片、8个半导体裸片、16个半导体裸片等)。在一些实施方案中，半导体裸片可为或可包含碳化硅半导体裸片(可称为碳化硅裸片)。碳化硅裸片可为高功率装置(例如，大于600V(例如，1200V))，其经配置以在高频(例如，大于1kHz，10kHz范围、100kHz、1MHz)切换。下文描述包含超过两个半导体裸片的模块(和封装)的更多实例。
引线框130包含引线框部分130-1到130-2。引线框部分130-1经耦合到半导体裸片10A的源极SA，且引线框部分130-3经耦合到半导体裸片10B的源极SB。引线框部分130-2经耦合到半导体裸片10A的栅极GA和半导体裸片10B的栅极GB(又可称为裸片栅极导体(例如，裸片栅极输入导体))。因此，半导体裸片10A和半导体裸片10B经电耦合到相同引线框部分130-2。可通过引线框部分130-2经由相同信号切换(例如，驱动、触发)半导体裸片10A的栅极GA和半导体裸片10B的栅极GB。引线框部分130-2可称为共同栅极导体(例如，共同栅极输入导体)，因为栅极GA、GB两者经耦合到引线框部分130-2。
外封装120包含使用通孔126电耦合到引线框部分130-2的栅极流道124。因此，半导体裸片10A和半导体裸片10B通过栅极流道124和通孔126电耦合，通孔126经耦合到引线框部分130-2。可通过栅极流道124经由相同信号切换半导体裸片10A的栅极GA和半导体裸片10B的栅极GB。再者，半导体裸片10A、10B可并联连接且并联切换。以虚线说明栅极流道124和通孔126，因为一或多个元件可不在与图1A中展示的切口(或本文中展示的其它切口)相同的平面上。
在一些实施方案中，栅极流道124可包含在金属层中。在一些实施方案中，栅极流道124可包含在衬底(未展示)内的金属层中。在一些实施方案中，栅极流道124经导电耦合到共同栅极导体CG且完全包含在外封装120中。
内封装110(及其元件)及外封装120(及其元件)经界定使得半导体裸片10A和半导体裸片10B可同时切换(例如，大体上同时)。具体来说，半导体裸片10A、10B、引线框部分130-2、通孔126和栅极流道124的定向可经界定使得半导体裸片10A、10B可同时切换。同时切换可在可明显比切换频率的周期短的时段内(例如，在几微秒内(例如，在一微秒内))执行。例如，可在明显比切换频率的周期短(例如，至少短2倍、短10倍)的时段内大体上同时执行包含在模块100中的半导体裸片10A、10B(或在一些实施例中，超过两个裸片)的切换。
如在图1A中展示，半导体裸片10A的栅极GA之间的导电路径CA的长度与半导体裸片10B的栅极GB的导电路径CB的长度相同。导电路径CA横穿引线框部分130-2和通孔126两者。导电路径CA从栅极GA的表面(例如，如图1A中定向的底部表面)和栅极流道124的表面(例如，如图1A中定向的顶部表面)延伸。导电路径CB以与导电路径CA成镜像的方式配置。
如图1A中由虚线Q2展示的栅极流道124居于栅极GA、GB之间的中心。栅极流道124的第一部分经安置在栅极GA的下方，且栅极流道124的第二部分经安置在栅极GB的下方。
如在图1A中展示，半导体裸片10A、10B两者以相同方向定向。具体来说，半导体裸片10A、10B的栅极GA、GB和源极SA、SB分别面向向下方向且耦合到引线框130。栅极GA、GB和源极SA、SB在相应的半导体裸片10A、10B的底侧上。
相应的半导体裸片10A、10B的漏极DA、DB面向向上方向，在相应的半导体裸片10A、10B的顶侧上。漏极DA、DB经耦合到导电间隔件15A、15B。一或多个间隔件15A、15B可通过内封装110的模制件112的顶部表面暴露。在一些实施方案(虽然未展示)中，一或多个间隔件15A、15B可暴露使得外封装120的一或多个组件可导电耦合到一或多个间隔件15A、15B。就模制件112讨论此申请的许多实施例，但在一些实施方案中，可使用任何类型的绝缘体，例如环氧树脂、模制件、灌注件及/或等等。
在一些实施方案中，间隔件15A、15B可经实施为单个间隔件或超过两个间隔件。在一些实施方案中，间隔件的数量可小于或大于半导体裸片的数量。在一些实施方案中，间隔件可包含铜或可包含铜材料。在一些实施方案中，间隔件可为或可包含铜钼。
虽然未展示，但在一些实施方案中，内封装110可去掉间隔件。在此类实施方案中，一或多个半导体裸片10A、10B的顶侧(或耦合到一或多个半导体裸片10A、10B的导电层)可通过模制件112暴露。
在一些实施方案中，夹片(未展示)可安置在内封装110内。在此类实施方案中，夹片的第一部分(例如，其底部表面)可经耦合到一或多个半导体裸片10A、10B的顶部表面。夹片的第二部分可通过内封装110的底部表面暴露。结合图6和7描述关于此实施方案的更多细节。
如在图1A中展示，半导体裸片10A、10B和间隔件15A、15B至少部分地囊封在内封装110的模制件112内。在此实施方案中，内封装110完全囊封在外封装120的模制件122内。
如图1B中由虚线Q3展示，栅极流道124居于栅极GA、GB之间的中心。具体来说，栅极GA(例如，面向虚线Q3的内边缘)与虚线Q3之间的距离与栅极GB(例如，面向虚线Q3的内边缘)与虚线Q3之间的距离相同。包含栅极GA的半导体裸片10A的侧面向(例如，直接面向，没有半导体裸片的中介部分)包含栅极GB的半导体裸片10B的侧。
相应的半导体裸片10A、10B的源极SA、SB比栅极GB、GA更远离栅极流道124。具体来说，半导体裸片10A、10B的源极SA、SB是在相应的半导体裸片10A、10B的远侧(相对于栅极GA、GB)，如在图1B中展示。
半导体裸片10A、10B可为或可包含高侧晶体管或低侧晶体管。例如，半导体裸片10A、10B的两者可为高侧晶体管。
在一些实施方案中，本文描述的模块100可与烧结工艺(例如，银烧结工艺)兼容，其中使用烧结材料和工艺形成组件之间(例如，引线框130与半导体裸片10A、10B之间)的界面。在一些实施方案中，在与碳化硅裸片相关联的高结温度的情况下，可能期望烧结界面，其可涉及固体材料在热和高压下聚结。烧结界面可具有预期的热性能、可靠性及/或温度系数(相对于例如焊接及回流界面)。
图1A中展示的封装中封装配置可与烧结界面特别兼容。具体来说，图1A中展示的封装中封装配置可导致内封装110内的界面(例如，半导体裸片10A、10B与间隔件15A、15B之间的界面、半导体裸片10A、10B与引线框部分130之间的界面)可在处理期间与形成于外封装120内的界面(例如，引线框部分130与通孔126之间的界面、通孔126与栅极流道124之间的界面)隔离(例如，分离)。因此，模块100可具有预期的倾斜控制、高产率及/或预期的应力/可靠性。封装中封装配置具有胜过可包含也可使用焊接和回流工艺形成的组件堆叠之间的多个堆叠界面(例如，超过五个堆叠界面)的单个封装堆叠的优点。
在一些实施方案中，说明为引线框130的部分的导电部分可经安置在内封装110的外侧。在一些实施方案中，说明为引线框130的部分的导电部分可包含在衬底(在图1A或1B中未展示)中。
在一些实施方案中，除了半导体裸片10A、10B以外，二极管装置(例如，二极管半导体装置)可包含在内封装110中。在其中包含在半导体裸片10A、10B的晶体管装置中的主体二极管不足以用于特定电路应用的情形中，二极管装置可包含在模块100中。在一些实施方案中，模块100可包含多个二极管装置。在一些实施方案中，模块100可包含1:1比例的二极管装置和晶体管装置。在一些实施方案中，模块100可包含大于或小于1:1(例如，1:2、2:1)比例的二极管装置和晶体管装置。
虽然未在图1A或1B中展示，但模块100可包含多个衬底。例如，在一些实施方案中，模块100可为双冷模块，其中第一衬底(未展示)在半导体裸片10A、10B(及内封装110)的第一侧上(例如，上方)，且第二衬底(未展示)在半导体裸片10A、10B(及内封装110)的第二侧上(例如，下方)。下文结合至少一些图描述与多个衬底相关的更多细节。
图2A到2D是说明内封装的组件(例如，层)的各种平面图的图。图2E是说明复合堆叠中的图2A到2D中展示的组件的平面图的图。在这些图中，一些组件展示为透明的，使得可观看到元件。复合堆叠的组件如结合例如图1A和1B描述排序。视图说明内封装的组件的布局(例如，图案)。图2A到2E涉及四(4)个半导体裸片(例如，MOSFET)配置，其中半导体裸片的栅极侧边缘具有菱形布局(可称为菱形配置)。在一些视图中，对半导体裸片的子组仅标记一些部分。
图2A说明与引线框230(图2B中展示)的形状大致对应的占据区202(以虚线表示)的平面图。在一些实施方案中，占据区202可与包含在直接接合的金属衬底(例如，直接接合的铜(DBC)衬底)上的金属(例如，铜)内的布局的形状对应。占据区202可为模制之后内封装的底侧占据区。占据区202可与可包含烧结表面的堆叠的区域对应。
图2B说明具有半蚀刻区域的引线框230的平面图。如在图2A及2B中展示，引线框230(及占据区202)包含栅极突出部。一个此种栅极突出部的实例是栅极突出部231A。栅极突出部中的每一者可经配置以耦合到半导体裸片的栅极(在图2C中展示)。栅极突出部231A可为或可包含栅极接触件。突出部从共同栅极导体CG(也可称为中心栅极接触件)延伸。在此实施方案中，共同栅极导体CG具有矩形形状。引线框230也包含源极部分232A，其经配置以耦合到半导体裸片的源极。
图2C说明待耦合到引线框230的半导体裸片(统称为半导体裸片20)的布局。如在图2C中展示，例如，半导体裸片20A相对于半导体裸片20B成一定角度(例如，垂直)对准，半导体裸片20B邻近于半导体裸片20A。对准是基于从相应的半导体裸片20A、20B的每一者的源极S到栅极G的虚线R1和R2。在此实施方案中，半导体裸片20A与半导体裸片20B垂直对准。因此，半导体裸片20A的边缘EA不平行于半导体裸片20B的边缘EB，半导体裸片20B邻近于半导体裸片20A。但是，半导体裸片20A的边缘EA具有平行于半导体裸片20C及/或与之对准的边缘。在一些实施方案(未展示)中，半导体裸片20A的边缘EA可不平行于且不垂直于半导体裸片20B的边缘EB。半导体裸片20沿着相同平面对准(或安置在相同平面内)。
半导体裸片20A的栅极G经配置以耦合到引线框230的栅极突出部231A。半导体裸片20A的源极S经配置以耦合到引线框230的源极部分232A。在此实施方案中，半导体裸片20(例如，半导体裸片20A、半导体裸片20B)的每一者的栅极G面向半导体裸片20的中心部分C，使得其可经耦合到共同栅极导体CG。
在此实施方案中，半导体裸片20A围绕共同栅极导体CG的纵轴J1而与半导体裸片20C成镜像(例如，纵轴平分)。类似地，半导体裸片20B围绕共同栅极导体CG的纵轴J1而与半导体裸片20D成镜像。
图2D是说明包含在图2C中展示的半导体裸片上方的顶部表面中的部分250的图。在一些实施方案中，图2D中展示的部分250可为漏极接触件或间隔件。如在图2D中展示，部分250具有背对中心部分的突出部或突片。
如在图2E中展示，栅极经由栅极突出部(例如，栅极突出部231A)耦合到共同栅极导体CG。通孔或其它金属层可经耦合到共同栅极导体CG，使得半导体裸片20可经触发以同时(例如，大体上同时)切换。半导体裸片20的每一者的栅极G与共同输入导体CG(例如，共同输入导体CG的中心)之间的导电路径的长度可为相同的。半导体裸片20的每一者的栅极G与接触共同栅极导体CG且通过其切换半导体裸片20的导体(例如，通孔、流道)之间的导电路径的长度可为相同的。共同栅极导体CG居于半导体裸片20的裸片栅极导体G之间的中心。在一些实施方案中，至少一个半导体裸片20的裸片栅极导体G相对于共同栅极导体CG定向，使得裸片栅极导体G与共同栅极导体CG之间的导电路径的长度最小化。
图3A到3D是说明内封装的变型的组件(例如，层)的各种平面图的图。图3E是说明复合堆叠中的图3A到3D中展示的组件的平面图的图。图3A到3E中的标记与图2A到2E中的标记相同，因为元件是相同的，但内封装的组件的布局(例如，图案)是不同的。因此，上文结合图2A到2E描述的一些特征不再结合图3A到3E予以重复。在图3A到3E中展示的配置中，半导体裸片的栅极侧边缘呈平行或矩形布局(可称为矩形配置)。矩形布局可包含正方形局部。
图3A说明与引线框230(图3B中展示)的形状大致对应的占据区202(以虚线表示)的平面图。
图3B说明具有半蚀刻区域的引线框230的平面图。如在图3A和3B中展示，引线框230(及占据区202)包含栅极突出部(例如，栅极突出部231A)和源极部分(例如，源极部分232A)。栅极突出部的每一者可经配置以耦合到半导体裸片的栅极(在图3C中展示)。突出部从共同栅极导体CG延伸。在此实施方案中，共同栅极导体CG具有矩形形状或长形形状。在此实施方案中，共同栅极导体CG可为安置在一对邻近半导体裸片之间的流道。在此实施方案中，共同栅极导体CG可为将封装分成两个半部的流道。在此实施方案中，共同栅极导体CG具有接触区域235(例如，突出部)，其包含在半导体裸片的中心部分中。
图3C说明待耦合到引线框230的半导体裸片(统称为半导体裸片20)的布局。如在图3C中展示，例如，半导体裸片20A平行于半导体裸片20B而对准，半导体裸片20B邻近于半导体裸片20A。对准是基于从相应的半导体裸片20A、20B的每一者的源极S到栅极G的虚线R1和R2。在此实施方案中，半导体裸片20A的边缘EA平行于半导体裸片20B的边缘EB，半导体裸片20B邻近于半导体裸片20A。半导体裸片20A的边缘EA具有平行于半导体裸片20C及/或与之对准(在封装的相对侧上)的边缘。半导体裸片20A围绕共同栅极导体CG的纵轴J1而与半导体裸片20C成镜像(例如，纵轴平分)。类似地，半导体裸片20B围绕共同栅极导体CG的纵轴J1而与半导体裸片20D成镜像。
图3D是说明包含在图3C中展示的半导体裸片上方的顶部表面中的部分250的图。
如在图3E中展示，栅极经由栅极突出部(例如，栅极突出部231A)耦合到共同栅极导体CG。通孔或其它金属层可经耦合到共同栅极导体CG的接触区域235，使得半导体裸片20可经触发以同时(例如，大体上同时)切换。半导体裸片20的每一者的栅极G与共同输入导体CG(例如，共同输入导体CG的中心线)之间的导电路径的长度可为相同的。半导体裸片20的每一者的栅极G与共同输入导体CG的接触区域235(例如，共同输入导体CG的中心)之间的导电路径的长度可为相同的。在此实施方案中，半导体裸片20(例如，半导体裸片20A、半导体裸片20B)的每一者的栅极G面向半导体裸片20的共同栅极导体CG，使得其可经耦合到共同栅极导体CG。
图4A到4L是说明内封装的变型的组件(例如，层)的各种平面图的图。图4A到4L涉及四(4)个半导体裸片(例如，MOSFET)配置，其中半导体裸片20以U形配置布置。
图4A说明内封装的一个侧(例如，栅极G和源极S侧)的占据区202(以虚线展示)的平面图，且图4B说明内封装的另一侧(例如，漏极侧)的占据区203(以虚线展示)的平面图。图4A中展示的占据区202一般可与引线框230(例如，在图4F中展示)对应。标记占据区的源极S部分和栅极G部分。图4L中展示与引线框230的底侧对应的占据区202的透视图。
图4B中展示的占据区203一般可与夹片290A、290B(例如，在图4C中展示)对应。占据区203与漏极D部分对应。图4D说明在卷盘中时包含在夹片组(例如，夹片对)中的夹片290A、290B。在图4C和4D中标注夹片290A、290B的半蚀刻部分292。
图4E到4I是说明与图4A到4D相关联的内封装的变型的组件(例如，层)的各种平面图的呈单元阵列(例如，2×2单元阵列)的图。图4E说明具有半蚀刻区域237和单元间(例如，胞元间)连杆234的引线框230。在图4K中展示具有半蚀刻区域237的引线框230(单个化引线框)的顶侧的透视图。在图4K中还展示隐藏的连杆238(例如，将囊封在模制件内)和暴露的连杆239(例如，将通过模制件暴露)。隐藏的连杆238经安置在比安置暴露的连杆239所沿着的平面更低的平面中。在图4L中展示半蚀刻裸片附接垫(DAP)锁件236。
图4E和4K说明共同栅极导体CG。在此实施方案中，与共同栅极导体CG相关联的栅极G接触件沿着使用具有标记为F1的两个箭头的组合虚点线展示的U形定向。图4E和4K说明半导体裸片20(在图4G中展示为半导体裸片20A到20D)的源极S接触件和栅极G接触件相对于共同栅极导体CG的位置和定向。
图4F说明接合层232(仅标记一些部分)，半导体裸片20(例如，半导体裸片20的栅极G和源极S)可通过接合层232耦合到引线框230。接合层232可包含例如焊料、可烧结的材料及/或等等。
图4G说明经由接合层232耦合到引线框230的半导体裸片20。半导体裸片20经对准使得半导体裸片20的栅极G安置在半导体裸片20的源极S与共同栅极导体CG之间。
由于共同栅极导体CG的形状，半导体裸片20A经对准使得半导体裸片20A的栅极G和源极S沿着线Y1对准，线Y1垂直于线Y2，半导体裸片20B的栅极G和源极S沿着线Y2对准。半导体裸片20A的栅极G和源极S经对准(沿着线Y2)而平行于半导体裸片20C的栅极G和源极S(其沿着线Y3对准)。半导体裸片20D经对准使得半导体裸片20D的栅极G和源极S沿着线Y4对准，线Y4垂直于线Y3，半导体裸片20C的栅极G和源极S沿着线Y3对准。
半导体裸片20A(围绕轴J1)相对于半导体裸片20C翻转(例如，成镜像)。具体来说，半导体裸片20A、20C的栅极G邻近于(例如，接近)共同栅极导体CG。半导体裸片20A、20C的源极S经安置在共同栅极导体CG的远端。
图4H说明接合层233(仅标记一些部分)，半导体裸片20(例如，半导体裸片20的漏极D)可通过接合层233耦合到夹片290A、290B(在图4I中展示)。接合层233可包含例如焊料、可烧结的材料及/或等等。图4I说明夹片290A、290B围绕线J1成镜像。夹片290A经耦合到一对半导体裸片20C、20D。夹片290B经耦合到一对半导体裸片20A、20B。
图4J是说明与结合图4A到4I、4K和4L描述的层对应的单个半导体裸片的层的图。
图5A是说明内封装的组件(例如，层)的平面图的图。内封装的内部分412的布局大体上与(例如)图2E中展示的组件的菱形布局相同。内封装包含耦合到引线框430的半导体裸片40。内封装具有与引线框430的形状大致对应的占据区402(以虚线表示)。
在此实施方案中，二极管装置460经电耦合到半导体裸片40。在此实施方案中，一对二极管装置460经电耦合(例如，经由引线框部分430-1电耦合)到内部分412的一个侧(例如，共同栅极导体CG的右侧)上的一对半导体裸片40。图5A中展示的配置包含安置在内封装的内部分412外侧(例如，沿着围绕内部分412的周边)的二极管装置460。半导体裸片40经安置在二极管装置460对与共同栅极导体CG之间。二极管装置460和半导体裸片40经安置在相同平面内(例如，沿着相同平面对准)。
图5B是说明图5A中展示的内封装的组件(例如，层)的变型的平面图的图。在此实施方案中，二极管装置460中的一者经电耦合(例如，经由引线框部分430-2电耦合)到半导体裸片40中的一者。
图5C是说明图5A中展示的内封装的组件(例如，层)的变型的平面图的图。此实施方案包含耦合到引线框430-4的一部分的间隔件470。二极管460的至少一部分和半导体裸片40的至少一部分经安置在共同栅极导体CG与间隔件470之间。
图5D是说明图5B中展示的内封装的组件(例如，层)的变型的平面图的图。此实施方案包含耦合到如在图5C中展示的引线框430-4的一部分的间隔件470。
图5E是说明图5B中展示的内封装的组件(例如，层)的变型的平面图的图。在此实施方案中，两个二极管与每一半导体裸片40相关联。此实施方案是基于U形配置。此实施方案也包含夹片490A、490B。
如上文描述，在例如其中包含在半导体裸片的晶体管装置中的主体二极管不足以用于特定电路应用的情形中，二极管装置可包含于在图5A到5D中展示和描述的内封装中。虽然在图5A到5D中展示为菱形配置，但是，半导体裸片可经界定成矩形配置或U形配置。在一些实施方案中，内封装可包含1:1比例的二极管装置和晶体管装置。在一些实施方案中，内封装可包含大于或小于1:1(例如，1:2、2:1)比例的二极管装置和晶体管装置。
图6到8是说明包含安置在封装120(例如，外封装)内的封装110(例如，内封装，子模块)的模块100的组件的侧部横截面视图的图。许多元件标记为与图1A展示的相同。图6到8可包含半导体裸片的任何配置(例如，矩形、U形、菱形)。
如在图6中展示，内封装110经耦合到衬底780。衬底780是直接接合的金属衬底(例如，直接接合的铜(DBC)衬底)。衬底780可包含例如一或多个金属层和一或多个电介质层。在一些实施方案中，衬底780可包含安置在直接接合的铜(DBC)衬底中的第一导体与第二导体之间的电介质。在此实施方案中，衬底780包含金属层780A、电介质780B和金属层780C。金属层780A、780C中的一或多者可如在图2A、3A中展示般图案化。
内封装110经耦合到衬底780。具体来说，内封装110可经由接合层792耦合到衬底780的金属层780A。接合层792可为或可包含烧结层、焊接层及/或等等。
如在图6中展示，内封装110的顶侧经由夹片790(例如，夹片的部分793)耦合到衬底780。具体来说，在此实施方案中，内封装110经由夹片790耦合到衬底780的金属层780A。夹片790(例如，夹片790的部分794)经由接合层791耦合到内封装110的顶侧，接合层791可为或可包含烧结层、焊接层及/或等等。
如在图6中展示，引线795延伸到外封装120的外侧(例如，暴露在外封装120外侧)。引线795经由衬底780(例如，衬底780的金属层780A)电耦合到内封装110及/或夹片790。
虽然未在图6中展示，但额外衬底可包含在模块100中。具体来说，可与衬底780相同或不同的额外衬底可经耦合到例如夹片790的顶侧(例如，部分794)。此类实施方案可称为双侧冷却实施方案，这是因为双衬底可实现顶侧和底侧冷却。在图7中展示此种实施方案。
在图7中展示的图中，模块100是双侧冷却实施方案。具体来说，衬底780(第一衬底)在模块100的底侧上，且衬底785在模块100的顶侧上。在此实施方案中，衬底785不包含金属层且仅包含电介质层。在一些实施方案中，衬底785可包含一或多个金属层。
在此实施方案中，衬底780的电介质780B包含开口780O，流体可移动通过开口780O以促进冷却。衬底785也包含此类开口785O。在一些实施方案中，开口可包含于衬底的仅一者(例如，衬底785或衬底780)中。在一些实施方案中，可从衬底780、785两者去掉开口。
在图7中展示的实施方案中，夹片790具有不同于图6中展示的夹片790的形状。具体来说，图7中展示的夹片790具有增大(例如，最大化)与衬底785的接触的形状。具体来说，夹片790具有沿着衬底785的底部表面延伸的第一部分(例如，部分794(顶部部分))和从夹片向下(且与第一部分垂直对准)延伸到衬底780的第二部分(例如，部分793(垂直部分))。
虽然未在图6或7中展示，但在一些实施方案中夹片790可包含在内封装110中。在此类实施方案中，夹片790的部分794的底部表面可使用例如接合层791耦合到半导体裸片15A、15B的顶部表面。同样地，在此类实施方案中，夹片790的一部分(例如，部分793的底部表面)可通过内封装110的底部表面暴露，使得夹片790可经耦合到例如衬底780。在其中夹片790包含在内封装110中的实施方案中，可去掉一或多个间隔件15A、15B。在其中夹片790包含在内封装110中的一些实施方案中，一或多个间隔件15A、15B可安置在内封装110内且经耦合到夹片790的部分794的顶侧。
图8说明模块100的变型，其是双侧冷却实施方案。如在图8中展示，模块100包含经由接合层791耦合到内封装110的顶侧的衬底787(例如，T覆层)。衬底787可包含例如一或多个金属层和一或多个电介质层。在一些实施方案中，衬底787可包含安置在直接接合的铜(DBC)衬底中的第一导体与第二导体之间的电介质。在此实施方案中，衬底780包含金属层787A、电介质787B和金属层787C。金属层787A、787C中的一或多者可经图案化。衬底787具有比衬底780的长度T3更长的长度T1。衬底787具有比衬底780的厚度T4更大的厚度T2。
在一些实施方案中，本文(例如，在图6到8中)描述的一或多个衬底中的一或多个金属层可具有不同于一或多个其它金属层(在相同衬底或不同衬底内)的厚度。在一些实施方案中，本文(例如，在图6到8中)描述的一或多个衬底中的一或多个电介质层可具有不同于一或多个其它电介质层(在相同衬底或不同衬底内)的厚度。
图9A到9D说明制造本文描述的内封装(例如，内封装110)的至少一部分的方法。如在图9A中展示，可界定(例如，形成)导电金属层930(例如，在衬底上，模压成引线框)。导电金属层930可包含共同栅极导体CG。
半导体裸片30可经电耦合到导电金属层930。在一些实施方案中，半导体裸片30可以倒装芯片配置耦合(其中源极和栅极向下(例如，耦合到导电金属层930))。半导体裸片30的栅极可经耦合到共同栅极导体CG，且半导体裸片30的源极可经耦合到导电金属层930的其它部分。导电金属层930及半导体裸片30可经配置使得距用于经由导电金属层930切换半导体裸片30的端子(例如，共同端子)的距离(例如，导电路径)可为相同的。
如在图9C中展示，导电金属层940(例如，厚铜层引线、烧结层、间隔件、T覆层)(使用虚线说明且说明为透明层)可经耦合到半导体裸片30的漏极(例如，在半导体裸片的顶侧上)。在此实施方案中未说明衬底。
如在图9D中展示，模制件912(使用虚点线说明且说明为透明层)可用于囊封组件(例如，半导体裸片30、导电金属层930、导电金属层940)。在一些实施方案中，共同栅极导体CG及/或导电金属层940的至少一些部分可通过模制件912暴露(例如，经由研磨暴露)。
图10A到10D说明图9A到9D中展示的制造方法的变型。在此变型中，经配置为间隔件950(例如，导电间隔件)的导电金属层经耦合到半导体裸片30的漏极(例如顶部部分)。在一些实施方案中，共同栅极导体CG及/或间隔件950的至少一些部分可通过模制件912暴露(例如，经由研磨暴露)。
使用矩形配置(例如在图3A到3E中展示)来实施图9A到10D中展示的制造方法，但是，也可实施菱形配置(例如在图2A到2E和5A到5D中展示)或U形配置(例如在图4A到4E和5E中展示)。
图11说明制造包含在模块内的内封装的方法。如在图11中展示，形成包含共同栅极导体的第一导电金属层(框S1100)。在一些实施方案中，第一导电金属层可包含在衬底内(例如，可包含在衬底的图案化金属层中)。在一些实施方案中，第一导电金属层可为引线框。
多个半导体裸片经耦合到第一导电金属层的共同栅极导体(框S1110)。多个半导体裸片可包含碳化硅裸片。多个半导体裸片可包含IGBT。在一些实施方案中，多个半导体裸片可相对于导电金属层的共同栅极导体呈菱形配置或布局。在一些实施方案中，多个半导体裸片可相对于导电金属层的共同栅极导体呈U形配置或布局。在一些实施方案中，多个半导体裸片可相对于导电金属层的共同栅极导体呈矩形配置或布局。在一些实施方案中，如本文描述，多个半导体裸片的栅极可以相同的导电路径长度耦合到共同栅极导体。
第二导电金属层经耦合到多个半导体裸片(框S1120)。在一些实施方案中，第二导电金属层可为间隔件。
第一导电金属层、半导体裸片和第二导电金属层至少部分地囊封在绝缘体内(框S1130)。在一些实施方案中，绝缘体可包含模制件、环氧树脂、灌注件及/或等等。在一些实施方案中，第二导电金属层的至少一部分可通过模制件暴露。在一些实施方案中，
第二导电金属层的至少一部分可经耦合到衬底及/或夹片。在一些实施方案中，导体可通过模制件暴露且接触共同栅极导体，使得可经由共同栅极导体切换多个半导体裸片。
在一些实施方案中，经由烧结材料耦合包含在包含内封装的模块内的至少一或多个组件。在一些实施方案中，一或多个二极管可包含在模块的内封装内。
图12是说明可使用本文描述的模块(和封装)实施的电路1200配置的图。如在图12中展示，电路包含高侧装置(例如，P型装置(装置P))和低侧装置(例如，N型装置(装置N))。在图12中标记装置的每一者的源极S、漏极D和栅极G。在图12中展示高侧端子(H-term)、低侧端子(L-term)和输出端子Out。电路1200为不具有输出Out的逆变器配置。装置的每一者(例如，装置P、装置N)可经界定在内封装内。
可例如在图13A到19D中展示的模块中实施图12中展示的电路1200。在许多这些配置中标记电路1200的端子(例如，引线)。装置的与低侧端子相关联的侧可称为装置的低侧，且装置的与高侧端子相关联的侧可称为装置的高侧。
图13A到13D是说明模块1300的各种视图的图。如在平面图图13A中展示，P型装置包含使用夹片1390P耦合到衬底1380的多个半导体裸片30P(例如，每对半导体裸片一个夹片)，且N型装置包含使用夹片1390N耦合到衬底1380的多个半导体裸片30N(例如，每对半导体裸片一个夹片)。在此实施方案中，半导体裸片30P、30N的漏极经由夹片1390P、1390N耦合到衬底。侧视图图13B是沿着图13A的方向N1观看，且侧视图图13C是沿着图13A的方向P1观看。图13D是沿着方向B1观看。经由耦合到共同栅极导体CG-P的引线接合部切换半导体裸片30P(半导体裸片30P的栅极)。经由耦合到共同栅极导体CG-N的引线接合部切换半导体裸片30N(半导体裸片30N的栅极)。
图14A和14B是说明模块1300的变型的各种视图的图。在此实施方案中，夹片1390P和1390N使用引线接合部替换。
图15A到17E是说明包含安置在外封装(例如，外封装120，例如在图6到8中的任一者中展示的外封装)内的内封装(例如，内封装110，例如在图2A到5D中的任一者中展示的内封装)的模块的各种视图的图。这些实施例中揭示的模块去掉引线接合部。换句话说，模块是无线模块。烧结材料、焊料及/或等等(其可包含在接合层中)可用于耦合任何组件对(例如，夹片、半导体裸片、间隔件、内封装、衬底等)。虽然图15A到17E以菱形配置的半导体裸片进行说明，但是也可实施矩形或U形配置。
图15A到15C是说明模块1500的各种视图的图。如在平面图图15A中展示，P型装置的内封装1510P包含使用夹片1590P耦合到衬底1580的多个半导体裸片50P(例如，每多个半导体裸片一个夹片)，且N型装置的内封装1510N包含使用夹片1590N耦合到衬底1580的多个半导体裸片50N(例如，每多个半导体裸片一个夹片)。在此实施方案中，半导体裸片50P、50N的漏极分别经由夹片1590P、1590N耦合到衬底。侧视图图15B是沿着图15A的方向N1观看，且侧视图图15C是沿着图15A的方向P1观看。
在此实施方案中，多个半导体裸片50P包含在内封装1510P中，其中半导体裸片50P呈菱形配置。经由共同栅极导体CG-P切换半导体裸片50P(半导体裸片50P的栅极)。
多个半导体裸片50N也包含在内封装1510N中，其中半导体裸片50N呈菱形配置。经由共同栅极导体CG-N切换半导体裸片50N(半导体裸片50N的栅极)。
图15D是说明衬底1580A的金属层图案1580A的图。图15E是说明衬底1580A的金属层图案1580A上的内封装1510P、1510N的布局的图。
图15F和15G是分别说明夹片1590P(经耦合到内封装1510P)的侧视图和平面图的图。虽然未展示，但夹片1590N(经耦合到内封装1510N)可具有与夹片1590P相同的形状。夹片1590P包含与半导体裸片50P的厚度大致对应的部分1593P。
如在图15A中展示，内封装1510N在平面内相对于内封装1510P偏移(例如，移位)。同样地，夹片1590P以相对于夹片1590N翻转的方向定向。
在此实施方案中，单个衬底1580经耦合到两个内封装1510N、1510P。虽然未展示，但在一些实施方案中，单独的衬底可经耦合到内封装的每一者。
图16A到16D是说明图15A到15G展示的模块1500的变型的各种视图的图。这些图中展示的模块1500可为也包含夹片1590N、1590P的双侧冷却实施方案。结合图15A到15G描述的元件不再结合此变型予以重复。
如在图16A到16C中展示，衬底1583经安置在模块1500的与衬底1580(在底侧上)相对的模块1500的侧(例如，顶侧)上。衬底1583可称为顶部衬底，且衬底1580可称为底部衬底。如在图16C中展示，例如，间隔件1520P经安置在衬底1583与夹片1590P之间。因此，垂直堆叠(沿着虚线U1从顶部到底部)可包含衬底1583、间隔件1520P、夹片1590P、内封装1510P和衬底1580。垂直堆叠(沿着虚线U2从顶部到底部)可包含衬底1583、夹片1590P和衬底1580。装置的低侧被类似地配置。
图16D说明接触分别耦合到内封装1510N、1510P的间隔件1520N、1520P的衬底1583的金属层1583A的图案化表面。通过成角度的拐角来说明将金属层1583A与内封装1510N、1510P及间隔件1520N、1520P的接触位置对准的标记(每个内封装4个标记)。在此实施方案中，单个衬底1583经耦合到两个内封装1510N、1510P的顶侧。虽然未展示，但在一些实施方案中，单独的衬底可经耦合到内封装的每一者来替代单个衬底1583。
图17A到17E是说明图15A到16D展示的模块1500的变型的各种视图的图。这些图中展示的模块1500可为去掉夹片1590N、1590P的双侧冷却实施方案。结合图15A到16D描述的元件不再结合此变型予以重复。
如在图17C中展示，例如，间隔件1520P经安置在衬底1583与内封装1510P之间。同样地，间隔件1522P经安置在间隔件1520P与衬底1580之间。因此，垂直堆叠(沿着虚线S1从顶部到底部)可包含衬底1583、间隔件1520P、内封装1510P和衬底1580。垂直堆叠(沿着虚线S2从顶部到底部)可包含衬底1583、间隔件1520P、间隔件1521P和衬底1580。间隔件1520P可称为顶部间隔件，且间隔件1521P可称为底部间隔件。装置的低侧被类似地配置。
图17D说明接触分别耦合到内封装1510N、1510P的间隔件1520N、1520P(其表面积大于图16A到16D展示的间隔件)的衬底1583的金属层1583A的图案化表面。通过成角度的拐角来说明将金属层1583A与内封装1510N、1510P及间隔件1520N、1520P的接触位置对准的标记(每个内封装4个标记)。在图17E中展示间隔件1520P和1521P的平面图。
在此实施方案中，单个衬底1583经耦合到两个内封装1510N、1510P的顶侧。虽然未展示，但在一些实施方案中，单独的衬底可经耦合到内封装的每一者来替代单个衬底1583。
图18A和18B是说明结合至少图17A到17E描述的模块1500的立体透视图的图。
图19A到19D是说明制造本文描述的装置的方法的图。并没有在每一视图中标记所有元件。如在图19A中展示，在此实施方案中，引线框结构可包含共同栅极导体CG-P、CG-N。共同栅极导体CG-P、CG-N可包含在衬底的金属层中，或可包含在内封装1510N、1510P中。图19B说明包含在模块1500中的内封装1510N、1510P和间隔件1521N、1521P。图19C说明经耦合到内封装1510N、1510P和间隔件1521N、1521P的间隔件1520N、1520P。图19D说明经耦合到间隔件1520N、1520P的衬底1583。在这些图中未展示模制层内的囊封。虽然图18A到19D以菱形配置的半导体裸片进行说明，但是也可实施矩形或U形配置。
应理解，在以上描述中，当元件(例如层、区、衬底或组件)称为在另一元件上、连接到、电连接到、耦合到或电耦合到另一元件时，其可直接在另一元件上，直接连接或耦合到另一元件，或可存在一或多个中介元件。相反，当元件称为直接在另一元件或层上、直接连接到或直接耦合到另一元件或层上时，不存在中介元件或层。虽然在整个具体实施方式中可能没有使用术语直接在……上、直接连接到或直接耦合到……，但是，展示为直接在……上、直接连接或直接耦合的元件可称为如此。可修改本申请的权利要求书(若有)以陈述说明书中描述或图中展示的例示性关系。
如在此说明书中使用，除非在上下文中明确地指示特定情况，否则单数形式可包含复数形式。空间相对术语(例如，在……上方(over、above)、上、在……下方(under、beneath、below)、下等等)希望涵盖除了图中描绘的定向外装置在使用或操作中的不同定向。在一些实施方案中，相对术语在……上方和在……下方可分别包含在……垂直上方和在……垂直下方。在一些实施方案中，术语邻近可包含侧向邻近于或水平邻近于。
本文描述的各种技术的实施方案可实施于(例如，包含于)数字电子电路中，或计算机硬件、固件、软件中或其组合中。方法的部分也可通过特殊用途逻辑电路(例如，FPGA(现场可编程门阵列)或ASIC(专用集成电路))执行，且设备也可实施为特殊用途逻辑电路。
实施方案可在计算系统中实施，所述计算系统包含后端组件(例如，作为数据服务器)，或包含中间件组件(例如，应用服务器)，或包含前端组件(例如，具有图形用户接口或网络浏览器的客户计算机，用户可通过所述图形用户接口或网络浏览器与实施方案交互)，或此类后端、中间件或前端组件的任何组合。组件可通过数字数据通信的任何形式或媒体(例如，通信网络)互连。通信网络的实例包含局域网(LAN)和广域网(WAN)，例如，因特网。
可使用各种半导体处理及/或封装技术来实施一些实施方案。可使用与半导体衬底相关联的各种类型的半导体处理技术来实施一些实施方案，包含但不限于(例如)硅(Si)、砷化镓(GaAs)、氮化镓(GaN)、碳化硅(SiC)及/或等等。
虽然描述的实施方案的特定特征已经如本文描述般说明，但所属领域的技术人员现将想到许多修改、替换、改变和等效物。因此，应理解，随附权利要求书希望涵盖落入实施方案的范围内的所有此类修改和改变。应理解，其已经仅通过实例(无限制)呈现，且可进行各种形式和细节的改变。除了互斥的组合外，本文描述的设备及/或方法的任何部分可以任何组合进行组合。本文描述的实施方案可包含所描述的不同实施方案的功能、组件及/或特征的各种组合及/或子组合。

Claims (14)

1.一种半导体装置设备，其包括：
封装，其包含：
共同栅极导体，
第一半导体裸片，其具有裸片栅极导体，及
第二半导体裸片，其具有裸片栅极导体；及
第一导电路径，其在所述共同栅极导体与所述第一半导体裸片的所述裸片栅极导体之间；及
第二导电路径，其在所述共同栅极导体与所述第二半导体裸片的所述裸片栅极导体之间；
所述第一导电路径具有大体上等于所述第二导电路径的长度的长度，
其中所述共同栅极导体居于所述第一半导体裸片和所述第二半导体裸片的所述裸片栅极导体之间的中心，所述第一半导体裸片的所述裸片栅极导体沿着所述第一半导体裸片的栅极侧边缘，所述第二半导体裸片的所述裸片栅极导体沿着所述第二半导体裸片的栅极侧边缘，所述第一半导体裸片的所述栅极侧边缘面向所述第二半导体裸片的所述栅极侧边缘。
2.根据权利要求1所述的半导体装置设备，其中所述第一半导体裸片和所述第二半导体裸片沿着相同平面对准且经电耦合到引线框，所述共同栅极导体包含在所述引线框中。
3.根据权利要求1所述的半导体装置设备，其中所述第一半导体裸片的所述裸片栅极导体相对于所述共同栅极导体定向，使得最小化所述第一导电路径的长度。
4.根据权利要求1所述的半导体装置设备，其中所述第一半导体裸片和所述第二半导体裸片沿着相同平面对准，所述第一半导体裸片具有平行于所述第二半导体裸片的边缘的边缘。
5.根据权利要求1所述的半导体装置设备，其中所述第一半导体裸片和所述第二半导体裸片沿着相同平面对准，所述第一半导体裸片具有不平行于且不垂直于所述第二半导体裸片的边缘的边缘。
6.根据权利要求1所述的半导体装置设备，其进一步包括：
多个半导体裸片，其包含所述第一半导体裸片、所述第二半导体裸片和具有裸片栅极导体的第三半导体裸片，
所述共同栅极导体居于所述多个半导体裸片的所述裸片栅极导体之间的中心。
7.根据权利要求1所述的半导体装置设备，其中所述第一半导体裸片和所述第二半导体裸片沿着相同平面对准，
所述半导体装置设备进一步包括：
多个二极管，其沿着相同平面对准且沿着包含所述第一半导体裸片和所述第二半导体裸片的所述封装外侧的周边安置。
8.根据权利要求1的半导体装置设备，其中所述封装为第一封装，
所述半导体装置设备进一步包括，
第二封装，其包含栅极流道，所述栅极流道经界定在包含电介质层和金属层的衬底的所述金属层内，所述第一封装经安置在所述第二封装内，所述栅极流道经导电耦合到包含在所述第一封装中的所述共同栅极导体，使得所述栅极流道中的位置与所述第一半导体裸片的所述裸片栅极导体之间的导电路径具有与所述栅极流道中的所述位置与所述第二半导体裸片的所述裸片栅极导体之间的导电路径大体上相同的长度。
9.一种半导体装置设备，其包括：
第一封装，其包含栅极金属流道；
第二封装，其经安置在所述第一封装中且包含：
第一碳化硅裸片，其具有裸片栅极导体，及
第二碳化硅裸片，其具有裸片栅极导体；及
第一导电路径，其在所述栅极金属流道与所述第一碳化硅裸片的所述裸片栅极导体之间；及
第二导电路径，其在所述栅极金属流道与所述第二碳化硅裸片的所述裸片栅极导体之间，
所述第一导电路径具有大体上等于所述第二导电路径的长度的长度，
其中所述栅极金属流道居于所述第一碳化硅裸片和所述第二碳化硅裸片的所述裸片栅极导体之间的中心，所述第一碳化硅裸片的所述裸片栅极导体沿着所述第一碳化硅裸片的栅极侧边缘，所述第二碳化硅裸片的所述裸片栅极导体沿着所述第二碳化硅裸片的栅极侧边缘，所述第一碳化硅裸片的所述栅极侧边缘面向所述第二碳化硅裸片的所述栅极侧边缘。
10.根据权利要求9所述的半导体装置设备，其进一步包括：
多个碳化硅裸片，其包含所述第一碳化硅裸片、所述第二碳化硅裸片和具有裸片栅极导体的第三碳化硅裸片，
引线框、所述第一碳化硅裸片、所述第二碳化硅裸片和所述第三碳化硅裸片经电耦合到引线框，所述栅极金属流道使用通孔电耦合到所述引线框，
所述通孔居于所述多个碳化硅裸片的所述裸片栅极导体之间的中心。
11.一种用于形成半导体装置设备的方法，其包括：
形成包含共同栅极导体的第一导电金属层；
将多个半导体裸片耦合到所述第一导电金属层的所述共同栅极导体，所述多个半导体裸片包含第一碳化硅裸片和第二碳化硅裸片；及
将所述第一导电金属层和所述半导体裸片的至少一部分囊封在绝缘体内，所述第一导电金属层包含所述共同栅极导体与所述第一碳化硅裸片的裸片栅极导体之间的第一导电路径和所述共同栅极导体与所述第二碳化硅裸片的裸片栅极导体之间的第二导电路径，所述第一导电路径具有大体上等于所述第二导电路径的长度的长度，
其中所述共同栅极导体居于所述第一碳化硅裸片和所述第二碳化硅裸片的所述裸片栅极导体之间的中心，所述第一碳化硅裸片的所述裸片栅极导体沿着所述第一碳化硅裸片的栅极侧边缘，所述第二碳化硅裸片的所述裸片栅极导体沿着所述第二碳化硅裸片的栅极侧边缘，所述第一碳化硅裸片的所述栅极侧边缘面向所述第二碳化硅裸片的所述栅极侧边缘。
12.根据权利要求11所述的方法，其中所述多个半导体裸片界定菱形配置。
13.一种用于形成半导体装置设备的方法，其包括：
形成封装，所述封装包含：
共同栅极导体，
第一半导体裸片，其具有裸片栅极导体，及
第二半导体裸片，其具有裸片栅极导体；
在所述共同栅极导体与所述第一半导体裸片的所述裸片栅极导体之间形成第一导电路径；及
在所述共同栅极导体与所述第二半导体裸片的所述裸片栅极导体之间形成第二导电路径，所述第一导电路径具有大体上等于所述第二导电路径的长度的长度，
其中所述共同栅极导体居于所述第一半导体裸片和所述第二半导体裸片的所述裸片栅极导体之间的中心，所述第一半导体裸片的所述裸片栅极导体沿着所述第一半导体裸片的栅极侧边缘，所述第二半导体裸片的所述裸片栅极导体沿着所述第二半导体裸片的栅极侧边缘，所述第一半导体裸片的所述栅极侧边缘面向所述第二半导体裸片的所述栅极侧边缘。
14.一种用于形成半导体装置设备的方法，其包括：
形成包含栅极金属流道的第一封装；
形成安置在所述第一封装中的第二封装，所述第二封装包含：
第一碳化硅裸片，其具有裸片栅极导体，及
第二碳化硅裸片，其具有裸片栅极导体；
在所述栅极金属流道与所述第一碳化硅裸片的所述裸片栅极导体之间形成第一导电路径；及
在所述栅极金属流道与所述第二碳化硅裸片的所述裸片栅极导体之间形成第二导电路径，所述第一导电路径具有大体上等于所述第二导电路径的长度的长度，
其中所述栅极金属流道居于所述第一碳化硅裸片和所述第二碳化硅裸片的所述裸片栅极导体之间的中心，所述第一碳化硅裸片的所述裸片栅极导体沿着所述第一碳化硅裸片的栅极侧边缘，所述第二碳化硅裸片的所述裸片栅极导体沿着所述第二碳化硅裸片的栅极侧边缘，所述第一碳化硅裸片的所述栅极侧边缘面向所述第二碳化硅裸片的所述栅极侧边缘。
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