CN206864460U - 一种防止芯片溢胶的封装结构 - Google Patents

一种防止芯片溢胶的封装结构 Download PDF

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CN206864460U
CN206864460U CN201720455743.7U CN201720455743U CN206864460U CN 206864460 U CN206864460 U CN 206864460U CN 201720455743 U CN201720455743 U CN 201720455743U CN 206864460 U CN206864460 U CN 206864460U
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刘庭
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本实用新型涉及一种防止芯片溢胶的封装结构，它包括基岛（5）和引脚（2），所述基岛（5）上设置有一环形围墙部（9），所述环形围墙部（9）的内侧设置有环形蓄胶槽（6），所述基岛（5）上通过装片粘结材料（8）设置有芯片（3），所述芯片（3）正面通过焊线（1）与引脚（2）实现电性相连，所述引脚（2）、基岛（5）和芯片（3）外围区域包封有封装填充料（4）。本实用新型一种防止芯片溢胶的封装结构，其环形蓄胶槽可以容置多余的装片粘结材料，环形围墙部可以防止装片粘结材料溢到芯片表面。

Description

一种防止芯片溢胶的封装结构
技术领域
本实用新型涉及一种防止芯片溢胶的封装结构，用于所有点胶或者画胶制程中用到的易发生扩散的装片粘合材料的控制，可以有效的控制易扩散装片材料的不规则流动性，属于半导体封装领域。
背景技术
传统的封装结构如图1所示，它包括基岛5和引脚2，基岛5上通过装片粘合材料6设置有芯片3，芯片3与引脚2之间通过焊线1相连接，基岛5、引脚2和芯片3外围包封有封装填充料4。
上述传统封装结构主要存在如下缺点：
框架上的画胶区域的基岛都为平面式的，若装片粘合材料量过多、粘稠度较低或者需要高温作业时，则容易发生胶材在基岛上扩散的问题，或者装片之后由于粘材过稀而溢到芯片表面，造成芯片污染、打线异常的问题。
实用新型内容
本实用新型所要解决的技术问题是针对上述现有技术提供一种防止芯片溢胶的封装结构，它在芯片底部基岛上开设环形蓄胶槽，环形蓄胶槽外围形成环形围墙部，环形蓄胶槽可以容置多余的装片粘结材料，环形围墙部可以防止装片粘结材料溢到芯片表面。即使在粘结材料量过多的情况下，多余的粘结材料也会顺着环形围墙部流到环形围墙部的外围。
本实用新型解决上述问题所采用的技术方案为：一种防止芯片溢胶的封装结构，它包括基岛和引脚，所述基岛上设置有一环形围墙部，所述环形围墙部的顶部高于基岛的正面，所述环形围墙部的内侧设置有环形蓄胶槽，所述环形蓄胶槽的底面低于基岛的正面，所述基岛上通过装片粘材料设置有芯片，所述芯片正面通过焊线与引脚实现电性相连，所述引脚、基岛和芯片外围区域包封有封装填充料。
所述环形蓄胶槽包围的基岛区域内设置有多个凹孔。
所述环形围墙部的外围设置有第二环形蓄胶槽。
与现有技术相比，本实用新型的优点在于：
1、芯片底部基岛上开设环形蓄胶槽，且环形蓄胶槽外围形成环形围墙部。如果装片后粘结材料有扩散，环形蓄胶槽可以容置多余的装片粘结材料。即使在胶量过多的情况下，多余的粘结材料也会顺着环形围墙部流到环形围墙部的外围，防止粘结材料溢到芯片表面污染芯片；
2、环形蓄胶槽内部区域设置有多个凹孔，可以减缓装片粘结材料的扩散，以及增加粘结材料与基岛的结合力，降低分层的风险。
3、第二环形蓄胶槽可以更优化多余粘结材料的蓄胶能力，进一步防止装片粘结材料的溢胶。
附图说明
图1为现有传统封装结构的示意图。
图2为本实用新型一种防止芯片溢胶的封装结构的示意图。
其中：
焊线1
引脚2
芯片3
封装填充料4
基岛5
环形蓄胶槽6
凹孔7
装片粘结材料8
环形围墙部9
第二环形蓄胶槽10。
具体实施方式
以下结合附图实施例对本实用新型作进一步详细描述。
如图2所示，本实施例中的一种防止芯片溢胶的封装结构，它包括基岛5和引脚2，所述基岛5上设置有一环形围墙部9，所述环形围墙部9的顶部高于基岛5的正面，所述环形围墙部9的内侧设置有环形蓄胶槽6，所述环形蓄胶槽6的底面低于基岛5的正面，所述基岛5上通过装片粘结材料8设置有芯片3，所述芯片3正面通过焊线1与引脚2实现电性相连，所述引脚2、基岛5和芯片3外围区域包封有封装填充料4；
所述环形蓄胶槽6包围的基岛5区域内设置有多个凹孔7。
所述环形围墙部9的外围设置有第二环形蓄胶槽10。
除上述实施例外，本实用新型还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本实用新型权利要求的保护范围之内。

Claims (3)

1.一种防止芯片溢胶的封装结构，其特征在于：它包括基岛（5）和引脚（2），所述基岛（5）上设置有一环形围墙部（9），所述环形围墙部（9）的顶部高于基岛（5）的正面，所述环形围墙部（9）的内侧设置有环形蓄胶槽（6），所述环形蓄胶槽（6）的底面低于基岛（5）的正面，所述基岛（5）上通过装片粘材料（8）设置有芯片（3），所述芯片（3）正面通过焊线（1）与引脚（2）实现电性相连，所述引脚（2）、基岛（5）和芯片（3）外围区域包封有封装填充料（4）。
2.根据权利要求1所述的一种防止芯片溢胶的封装结构，其特征在于：所述环形蓄胶槽（6）包围的基岛（5）区域内设置有多个凹孔（7）。
3.根据权利要求1所述的一种防止芯片溢胶的封装结构，其特征在于：所述环形围墙部(9)的外围设置有第二环形蓄胶槽(10)。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110335855A (zh) * 2019-07-10 2019-10-15 广东气派科技有限公司 一种改善焊接空洞的芯片封装结构
CN111540725A (zh) * 2020-07-10 2020-08-14 甬矽电子(宁波)股份有限公司 引线框架、方形扁平无引脚封装结构及封装方法
CN112563226A (zh) * 2019-02-22 2021-03-26 西安航思半导体有限公司 便于散热的dfn封装器件
CN112701054A (zh) * 2019-02-22 2021-04-23 西安航思半导体有限公司 电子产品用半导体器件的制造方法
CN115621212A (zh) * 2022-11-07 2023-01-17 合肥矽迈微电子科技有限公司 一种防溢的封装结构及其装片方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112563226A (zh) * 2019-02-22 2021-03-26 西安航思半导体有限公司 便于散热的dfn封装器件
CN112701054A (zh) * 2019-02-22 2021-04-23 西安航思半导体有限公司 电子产品用半导体器件的制造方法
CN112701054B (zh) * 2019-02-22 2022-07-19 西安航思半导体有限公司 电子产品用dfn半导体器件的制造方法
CN110335855A (zh) * 2019-07-10 2019-10-15 广东气派科技有限公司 一种改善焊接空洞的芯片封装结构
CN111540725A (zh) * 2020-07-10 2020-08-14 甬矽电子(宁波)股份有限公司 引线框架、方形扁平无引脚封装结构及封装方法
CN111540725B (zh) * 2020-07-10 2021-09-14 甬矽电子(宁波)股份有限公司 引线框架、方形扁平无引脚封装结构及封装方法
CN115621212A (zh) * 2022-11-07 2023-01-17 合肥矽迈微电子科技有限公司 一种防溢的封装结构及其装片方法

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