CN110335855A - 一种改善焊接空洞的芯片封装结构 - Google Patents
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Abstract
本发明涉及一种改善焊接空洞的芯片封装结构,包括芯片和引线框基岛,所述芯片通过焊接料固定在引线框基岛上,所述芯片和引线框基岛之间的焊接料厚度为15‑20μm,所述芯片正下方的引线框基岛上表面设有凹槽,所述凹槽的面积小于芯片的面积,所述凹槽的深度为15‑25μm。本发明在保持原有的封装结构的基础上,在芯片正下方的引线框基岛上表面设置凹槽,凹槽不影响原来的引线框基岛对芯片的支撑方式,所以芯片倾斜不会超标,焊接料爬高容易控制;另外凹槽的深度为15‑25μm,这样芯片下方凹槽处的焊接料厚度变成大于30μm,很好地解决了焊接空洞问题。
Description
技术领域
本发明涉及芯片封装技术领域,尤其涉及一种改善焊接空洞的芯片封装结构。
背景技术
一些芯片封装产品工作时电流大、功率高,工作温度也较高(会达到250度左右),要求芯片封装产品具有高散热性的特性,为了满足其高散热要求,使用的封装材料(塑封料、焊接料)都需要具有高导热性的特性,尤其是芯片底部的焊接料,连接了芯片和引线框基岛,芯片产生的热先传递到引线框基岛上,再散失到空气中,所以焊接料也是关键性的材料,高导热性的焊接料热导率一般要大于50W/(m.K),但是此类材料也有一些缺点,如图1所示,为现有技术中的一种芯片封装结构,包括引线框5、引线框基岛2、芯片1、金线7、焊接料3和塑封料6,现有技术中焊接料3厚度一般采用15-20μm,在烘烤固化焊接后,芯片1与引线框基岛2之间的焊接料3中会出现很多空洞,试验表明,芯片1与引线框基岛2之间焊接空洞面积与产品散热性呈明显的反比关系,这严重的影响了芯片封装产品的散热性,散热性差会导致产品异常,降低产品寿命,甚至直接失效。
为了减少焊接空洞,通过实验发现,当焊接料的用量要达到一定要求,既厚度大于30μm时,焊接空洞会明显降低,能满足散热要求。当焊接料的厚度大于30μm时,虽然解决了焊接空洞问题,但对后续封装工艺又产生了不利影响,由于焊接料厚度大,很容易在装片时出现芯片倾斜超标,严重影响焊接质量和产量,同时芯片倾斜也会造成芯片散热不均匀,影响散热稳定性;芯片边缘焊接料溢料超标,焊接料爬高控制困难,使产品的生产很不稳定,既造成了生产质量难以管控,又影响了产品的产能,有待改进。
发明内容
本发明的目的在于提供一种改善焊接空洞的芯片封装结构,既能解决焊接空洞问题,又能解决芯片倾斜超标的问题。
本发明是这样实现的:一种改善焊接空洞的芯片封装结构,包括芯片和引线框基岛,所述芯片通过焊接料固定在引线框基岛上,所述芯片和引线框基岛之间的焊接料厚度为15-20μm,所述芯片正下方的引线框基岛上表面设有凹槽,所述凹槽的面积小于芯片的面积,所述凹槽的深度为15-25μm。
其中,所述凹槽的深度为20μm。
其中,所述凹槽的侧面为斜面,与底面形成钝角。
其中,所述凹槽通过激光去材料的方法加工出来。
其中,所述引线框基岛的焊接面上还设有镀银层。
其中,所述凹槽的形状为圆形、方形或多边形。
其中,所述凹槽上开口的面积等于芯片面积的60%-90%。
本发明的有益效果为:本发明所述改善焊接空洞的芯片封装结构在保持原有的封装结构的基础上,在芯片正下方的引线框基岛上表面设置凹槽,凹槽的面积小于芯片的面积,芯片和引线框基岛之间的焊接料厚度为15-20μm,不影响原来的引线框基岛对芯片的支撑方式,所以芯片倾斜不会超标,即使完全倾斜,也不会超过15-20μm,符合装片要求,从而保证散热性能(散热均匀性),焊接时由于芯片边缘的焊接料较薄,焊接料爬高容易控制,溢料不易超标,使产品的生产稳定,质量易管控,不影响产能;另外凹槽的深度为15-25μm,这样芯片下方凹槽处的焊接料厚度变成大于30μm,很好地解决了焊接空洞问题,凹槽的面积越接近芯片的面积,焊接空洞问题就解决得越好,但也不能等于芯片的面积,这样芯片边缘无法得到足够的支撑,又会出现芯片倾斜超标的问题;所述凹槽具有锁紧作用,还能增强焊接料与引线框基岛的接触面积和结合力,使焊接料与引线框基岛更不易分离,提升产品的质量和可靠性;在布置焊接料时也更简单,不必设计特殊的化胶模式,可以直接采用简单的点胶就可以,既可以控制芯片边缘的焊接料厚度为15-20μm,又可以保证凹槽处的焊接料厚度大于30μm,控制方便。
附图说明
图1是现有技术中芯片封装结构的剖面结构示意图;
图2是本发明所述芯片封装结构的剖面结构示意图;
图3是本发明所述引线框基岛的剖面示意图;
图4是本发明所述引线框基岛的俯视图;
图5是本发明把焊接料点胶在引线框基岛上的结构示意图;
图6是本发明把芯片焊接在引线框基岛上的结构示意图;
图7是本发明所述引线框基岛实施例二的结构示意图;
图8是本发明把芯片焊接在引线框基岛实施例二上的结构示意图;
图9是本发明所述引线框基岛实施例三的结构示意图;
图10是本发明所述引线框基岛实施例四的结构示意图。
其中,1、芯片;2、引线框基岛;21、凹槽;3、焊接料;4、镀银层;5、引线框;6、塑封料;7、金线。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
作为本发明所述改善焊接空洞的芯片封装结构的实施例一,如图2至图6所示,包括芯片1和引线框基岛2,所述芯片1通过焊接料3固定在引线框基岛2上,所述芯片1和引线框基岛2之间的焊接料3厚度为15-20μm,所述芯片1正下方的引线框基岛2上表面设有凹槽21,所述凹槽21的面积小于芯片的面积,所述凹槽21的深度为15-25μm。本发明所述凹槽21的深度更优选值为20μm。
本发明所述改善焊接空洞的芯片封装结构在保持原有的封装结构的基础上,在芯片1正下方的引线框基岛2上表面设置凹槽21,凹槽21的面积小于芯片1的面积,芯片1和引线框基岛2之间的焊接料3厚度为15-20μm,不影响原来的引线框基岛2对芯片1的支撑方式,所以芯片1倾斜不会超标,即使完全倾斜,也不会超过15-20μm,符合装片要求,从而保证散热性能(散热均匀性),焊接时由于芯片1边缘的焊接料3较薄,焊接料3爬高容易控制,溢料不易超标,使产品的生产稳定,质量易管控,不影响产能;另外凹槽21的深度为15-25μm,这样芯片1下方凹槽21处的焊接料3厚度变成大于30μm,很好地解决了焊接空洞问题,凹槽21的面积越接近芯片1的面积,焊接空洞问题就解决得越好,但也不能等于芯片的面积,这样芯片边缘无法得到足够的支撑,又会出现芯片倾斜超标的问题,所以凹槽21上开口的面积等于芯片1面积的60%-90%,是比较合适的;所述凹槽21具有锁紧作用,还能增强焊接料3与引线框基岛2的接触面积和结合力,使焊接料3与引线框基岛2更不易分离,提升产品的质量和可靠性;在布置焊接料3时也更简单,不必设计特殊的化胶模式,可以直接采用简单的点胶就可以,既可以控制芯片1边缘的焊接料3厚度为15-20μm,又可以保证凹槽21处的焊接料3厚度大于30μm,控制方便。
相比现有技术中采用30μm以上厚度焊接料的芯片封装产品,本发明芯片1和引线框基岛2距离更近,有利于芯片1将热量传递到引线框基岛2上,并散失到外部环境中,所以散热性更好。
在本实施例中,所述凹槽21的侧面为斜面,与底面形成钝角(角度优选值为120-150度),即凹槽21为上大下小呈倒梯形,这样利于点胶时凹槽21内的空气被排出。
在本实施例中,所述凹槽21通过激光去材料的方法(烧蚀)加工出来。凹槽21深度可通过控制激光的运行电流以及烧蚀速度来实现精确控制。
在引线框基岛上制作15-25μm深度凹槽难度极大,采用引线框常规加工方法都无法达到精度要求,冲压工艺加工深度极难控制,因其加工偏差就能达到10-15μm;蚀刻工艺倒是可以做出较高精度的凹槽,但是蚀刻出来的凹槽边缘会有一些内凹,边缘内凹会造成点胶空洞,在后期焊接时形成更大的焊接空洞,也不合适。本申请人采用激光去材料的方法就完美解决了这个问题。
在本实施例中,所述凹槽21的形状为圆形,也可以为如图10所示的方形,或图9所示的多边形,当然也可以采用其它规则或不规则的形状。
作为本发明所述引线框基岛的实施例二,如图7和图8所示,所述引线框基岛2的焊接面上还设有镀银层4,镀银层4可以提高引线框基岛2的导电能力。假设镀银层4厚度为5μm,相应地凹槽21的加工深度也应加深5μm。
本发明所述引线框基岛的结构形式,应用范围广,不仅可以使用在高散热要求的产品,还能使用于其它类型产品的点胶工艺,利于控制芯片倾斜,改善溢料等问题。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (7)
1.一种改善焊接空洞的芯片封装结构,包括芯片和引线框基岛,所述芯片通过焊接料固定在引线框基岛上,所述芯片和引线框基岛之间的焊接料厚度为15-20μm,其特征在于,所述芯片正下方的引线框基岛上表面设有凹槽,所述凹槽的面积小于芯片的面积,所述凹槽的深度为15-25μm。
2.根据权利要求1所述改善焊接空洞的芯片封装结构,其特征在于,所述凹槽的深度为20μm。
3.根据权利要求1所述改善焊接空洞的芯片封装结构,其特征在于,所述凹槽的侧面为斜面,与底面形成钝角。
4.根据权利要求3所述改善焊接空洞的芯片封装结构,其特征在于,所述凹槽通过激光去材料的方法加工出来。
5.根据权利要求1所述改善焊接空洞的芯片封装结构,其特征在于,所述引线框基岛的焊接面上还设有镀银层。
6.根据权利要求1所述改善焊接空洞的芯片封装结构,其特征在于,所述凹槽的形状为圆形、方形或多边形。
7.根据权利要求1所述改善焊接空洞的芯片封装结构,其特征在于,所述凹槽上开口的面积等于芯片面积的60%-90%。
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CN113394180A (zh) * | 2021-06-10 | 2021-09-14 | 广东气派科技有限公司 | 通信用高频功放芯片的封装结构及其封装方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1174439A (ja) * | 1997-08-28 | 1999-03-16 | Sharp Corp | 樹脂モールドパッケージ |
US20060151862A1 (en) * | 2005-01-11 | 2006-07-13 | Siliconware Precison Industries Co., Ltd. | Lead-frame-based semiconductor package and lead frame thereof |
CN201681877U (zh) * | 2010-04-26 | 2010-12-22 | 江苏长电科技股份有限公司 | 下沉基岛露出型封装结构 |
CN206864460U (zh) * | 2017-04-27 | 2018-01-09 | 江苏长电科技股份有限公司 | 一种防止芯片溢胶的封装结构 |
-
2019
- 2019-07-10 CN CN201910621259.0A patent/CN110335855A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1174439A (ja) * | 1997-08-28 | 1999-03-16 | Sharp Corp | 樹脂モールドパッケージ |
US20060151862A1 (en) * | 2005-01-11 | 2006-07-13 | Siliconware Precison Industries Co., Ltd. | Lead-frame-based semiconductor package and lead frame thereof |
CN201681877U (zh) * | 2010-04-26 | 2010-12-22 | 江苏长电科技股份有限公司 | 下沉基岛露出型封装结构 |
CN206864460U (zh) * | 2017-04-27 | 2018-01-09 | 江苏长电科技股份有限公司 | 一种防止芯片溢胶的封装结构 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113394180A (zh) * | 2021-06-10 | 2021-09-14 | 广东气派科技有限公司 | 通信用高频功放芯片的封装结构及其封装方法 |
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