CN206388695U - 一种芯片的封装结构 - Google Patents

一种芯片的封装结构 Download PDF

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CN206388695U
CN206388695U CN201720059599.5U CN201720059599U CN206388695U CN 206388695 U CN206388695 U CN 206388695U CN 201720059599 U CN201720059599 U CN 201720059599U CN 206388695 U CN206388695 U CN 206388695U
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chip
glue
support plate
box dam
metal wire
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郭红梅
刘宇环
詹亮
谢建友
刘卫东
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Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型公开了一种芯片的封装结构,包括,载板、粘片胶、芯片、金属线、围坝、填充胶,所述载板上端固定设置有芯片,所述载板和芯片通过粘片胶连接,所述芯片和载板通过金属线电性连接,所述芯片周边设置有围坝,所述围坝内填充有填充胶,所述填充胶包裹粘片胶、芯片、金属线。该技术将晶圆减薄并划片成规定尺寸的芯片,通过粘片胶将芯片贴在载板上,通过金属线将芯片和载板连接,将胶水沿芯片外围划胶,形成围坝形状,向围坝内圈注填充胶,固化后最终形成具有独特封装工艺的封装结构;本工艺制作简单,缩短了加工周期,降低了加工成本。

Description

一种芯片的封装结构
技术领域
本实用新型涉及半导体芯片封装技术领域,具体涉及一种芯片的封装结构。
背景技术
现有的芯片的封装方法存在以下问题,为了保护芯片,目前芯片贴片打线后都要进行塑封工艺,塑封工艺需要投资模具,而且工艺复杂,加工周期长,成本高。
实用新型内容
本实用新型解决的技术问题在于克服现有技术的缺陷,提供一种芯片的封装结构。
在本实用新型的实施例中提供了一种芯片的封装结构,包括,载板、粘片胶、芯片、金属线、围坝、填充胶,所述载板上端固定设置有芯片,所述载板和芯片通过粘片胶连接,所述芯片和载板通过金属线电性连接,所述芯片周边设置有围坝,所述围坝内填充有填充胶,所述填充胶包裹粘片胶、芯片、金属线。
优选的,所述金属线为金线、合金线和铜线中任意一种。
优选的,所述填充胶与围坝高度平齐,填充胶材料为环氧树脂类材料。
优选的,所述围坝的材料为环氧树脂类材料,且所述围坝为矩形或任意形状的不规则封闭结构。围坝的尺寸可以根据芯片封装空间的大小和高度要求调整。
一种芯片的封装结构,具体按照以下步骤进行:
第一步:准备载板;
第二步:通过粘片胶贴芯片;
第三步:金属线键合,芯片通过金属线与载板电性连接;
第四步:划围坝胶,通过划胶在芯片周围形成围坝;
第五步:灌注填充胶。
本实用新型的有益效果:该技术将晶圆减薄并划片成规定尺寸的芯片,通过粘片胶将芯片贴在载板上,通过金属线将芯片和载板连接,将胶水沿芯片外围划胶,形成围坝形状,向围坝内圈注填充胶,固化后最终形成具有独特封装工艺的封装结构;本工艺制作简单,缩短了加工周期,降低了加工成本,跨越了传统的塑封工段,无需投资塑封模具,密封性好,应用范围广。
附图说明
图1为本实用新型的主视结构示意图;
图2为本实用新型的俯视结构示意图。
其中,载板1、粘片胶2、芯片3、金属线4、围坝5、填充胶6。
具体实施方式
如图1和图2所示,一种芯片的封装结构,包括,载板1、粘片胶2、芯片3、金属线4、围坝5、填充胶6,所述载板1上端固定设置有芯片3,所述载板1和芯片3通过粘片胶2连接,所述芯片3和载板1通过金属线4电性连接,所述芯片3周边设置有围坝5,所述围坝5内填充有填充胶6,所述填充胶6包裹粘片胶2、芯片3、金属线4。所述金属线4为金线、合金线和铜线中任意一种。所述填充胶6与围坝5高度平齐。所述围坝5的材料为环氧树脂类材料,且所述围坝5为矩形或任意形状的不规则封闭结构。
实施例:将晶圆减薄并划片成规定尺寸的芯片3,通过粘片胶2将芯片3贴在载板1上,通过金属线4将芯片3和载板1连接,用胶水沿芯片3外围划胶,形成围坝5形状,向围坝5内圈注填充胶6,固化后最终形成具有独特封装工艺的封装结构;
以上为本实用新型较佳的实施方式,本实用新型所属领域的技术人员还能够对上述实施方式进行变更和修改,因此,本实用新型并不局限于上述的具体实施方式,凡是本领域技术人员在本实用新型的基础上所作的任何显而易见的改进、替换或变型均属于本实用新型的保护范围。

Claims (4)

1.一种芯片的封装结构,包括,载板(1)、粘片胶(2)、芯片(3)、金属线(4)、围坝(5)和填充胶(6),其特征在于,所述载板(1)上端固定设置有芯片(3),所述载板(1)和芯片(3)通过粘片胶(2)连接,所述芯片(3)和载板(1)通过金属线(4)电性连接,所述芯片(3)周边设置有围坝(5),所述围坝(5)内填充有填充胶(6),所述填充胶(6)包裹粘片胶(2)、芯片(3)、金属线(4)。
2.根据权利要求1所述的一种芯片的封装结构,其特征在于,所述金属线(4)为金线、合金线和铜线中任意一种。
3.根据权利要求1所述的一种芯片的封装结构,其特征在于,所述填充胶(6)与围坝(5)高度平齐,所述填充胶(6)材料为环氧树脂类材料。
4.根据权利要求1或3任意一项所述的一种芯片的封装结构,其特征在于,所述围坝(5)的材料为环氧树脂类材料,且所述围坝(5)为矩形或任意形状的不规则封闭结构。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108328562A (zh) * 2018-02-28 2018-07-27 山东盛芯半导体有限公司 一种压力传感器封装结构与封装方法
WO2022126434A1 (zh) * 2020-12-16 2022-06-23 华为技术有限公司 一种芯片封装以及芯片封装的制备方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108328562A (zh) * 2018-02-28 2018-07-27 山东盛芯半导体有限公司 一种压力传感器封装结构与封装方法
CN108328562B (zh) * 2018-02-28 2024-05-17 山东盛芯电子科技有限公司 一种压力传感器封装结构的封装方法
WO2022126434A1 (zh) * 2020-12-16 2022-06-23 华为技术有限公司 一种芯片封装以及芯片封装的制备方法

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