CN205542766U - 电子元件 - Google Patents

电子元件 Download PDF

Info

Publication number
CN205542766U
CN205542766U CN201520967467.3U CN201520967467U CN205542766U CN 205542766 U CN205542766 U CN 205542766U CN 201520967467 U CN201520967467 U CN 201520967467U CN 205542766 U CN205542766 U CN 205542766U
Authority
CN
China
Prior art keywords
marking
circuit
electronic component
lid
photoresistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201520967467.3U
Other languages
English (en)
Inventor
K·方克
K·弗莫萨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Malta Ltd
Original Assignee
STMicroelectronics Malta Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Malta Ltd filed Critical STMicroelectronics Malta Ltd
Application granted granted Critical
Publication of CN205542766U publication Critical patent/CN205542766U/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/352—Working by laser beam, e.g. welding, cutting or boring for surface treatment
    • B23K26/359—Working by laser beam, e.g. welding, cutting or boring for surface treatment by providing a line or line pattern, e.g. a dotted break initiation line
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/0006—Working by laser beam, e.g. welding, cutting or boring taking account of the properties of the material involved
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/351—Working by laser beam, e.g. welding, cutting or boring for trimming or tuning of electrical components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Optics & Photonics (AREA)
  • Mechanical Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Laser Beam Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

本公开涉及电子元件。其中提供了一种电子元件(10)，包括：-至少一个电路(12)，具有前表面，以及位于所述至少一个电路(12)上的透光封装(14)；-光阻材料的盖状部件(24)，应用在所述前表面上；以及-所述元件(10)的标刻(M)，所述标刻被激光标刻(102)到所述光阻盖状部件(24)上，其中所述标刻(M)通过所述透光封装(14)可见。

Description

电子元件
技术领域
本公开涉及电子元件。
背景技术
由于多方面的原因，标刻(例如激光标刻)可应用于电子元件，这些原因例如：
-pin-1指示；
-追踪(trace)能力；
-指示制作信息，如厂商ID和车间ID；
-让元件例如为客户承载感兴趣的信息。
应用于具有透明封装的元件的标刻结果可能是由于例如缺乏对比度而很难辨认。
另外，具有透明封装的电子元件可能包括光感电路。保护不受潜在有害的光辐射(例如UV、IR和/或可见光辐射)可能是期望的特性。
实用新型内容
一个或多个是实施例的目标是提供上文所讨论的电子元件封装的改进。其中，本公开提供了一种电子元件(10)，包括：-至少一个电路(12)，具有前表面，以及位于所述至少一个电路(12)上的透光封装(14)；-光阻材料的盖状部件(24)，应用在所述前表面上；以及-所述元件(10)的标刻(M)，所述标刻被激光标刻(102)到所述光阻盖状部件(24)上，其中所述标刻(M)通过所述透光封装(14)可见。
在一个或多个实施例中该目标的实现得益于具有本公开提供的 上述电子元件的特征的如下方法。
一个或多个实施例还涉及相应电子元件(例如集成电路或IC)。
权利要求是结合一个或多个实施例提供的技术公开的不可分割的部分。
一个或多个实施例可提供在包括透明封装的电子元件中用于激光标刻和电路保护的解决方案，例如通过例如经由芯片粘贴工艺应用的“裸”硅盖(板)。
一个或多个实施例可提供用于激光标刻并同时具有充分的电路保护的多个稳健解决方案。
一个或多个实施例可涉及当应用在电路(例如ASIC)上时，通过半导体或金属盖状部件替换“顶部包封，glob top”材料。这可在元件顶部(即，在前表面)上提供标刻平台并同时提供光阻属性。
一个或多个实施例可产生更保形的工艺，其可证明在保形涂层重复性方面是更稳定的，同时提供改进的收益、设备性能和生产率(每小时单元数或UPH)。
一个或多个实施例可使得元件顶部标刻面积增加，因而元件能承载更多的数据量；从元件读取这些信息可更方便，更可能地，其中的元件(已经)安装在例如印刷电路板(PCB)的支持物上。
附图说明
参照附图将仅以示例的方式对一个或多个实施例进行描述，其中：
图1是根据实施例的电子元件的顶视图；
图2是沿图1中II-II线的截面图；以及
图3是根据一个或多个实施例的方法中的步骤的功能流程图。
具体实施方式
在接下来的描述中，将阐明一个或多个具体细节，旨在提供实施例的示例的深入理解。不需要一个或多个具体细节，或者用其他 方法、元件或材料等，可得到实施例。在另一些情况下，为了不模糊实施例的某些方面，已知的结构、材料或操作并未示出或进行具体描述。
在本描述的框架中提及的“一实施例”或“一个实施例”意在表明，涉及的实施例中所描述的特定配置、结构或特征被包含在至少一个实施例中。因此，在本描述的一个或多个方面出现的术语如“一实施例”或“一个实施例”并不必定涉及一个相同的实施例。另外，特定构造、结构或特征可在一个或多个实施例中被以任何合适的方式组合。
本文使用的参考内容仅为了方便而提供，因而并不限定实施例的保护程度或范围。
在提供电子元件如集成电路(IC)(如专用集成电路(ASIC))的标刻中可能产生多种问题。
这样的标刻可以是顶边标刻，即IC的顶部或上(前)侧的标刻，其与基底相反，而元件最终安置于基底上。印刷电路板或PCB是这样的安置基底的示例。
激光标刻是可能的标刻选项的示例。在激光标刻中，激光光束可被直接聚集到封装顶部表面上。激光标刻技术已经被广泛应用于传统的深色树脂(dark-resin)模制封装。深色树脂模制封装有效地烧制树脂顶部表面，产生褪色，因而产生创建标刻图案的对比图像。
不同元件例如UV(紫外线)传感器、运动MEMS(微机电系统)、环境MEMS、不同类型的光设备等可包括“透明”封装，即封装包括光辐射(即可见光、UV或IR范围内的光辐射)可透的材料。
在这方面，电路(如ASIC)的“顶部包封”保形覆盖可以是能处理高度限制的选项。具有光阻属性的顶部包封材料可被例如以混合胶的形式应用以覆盖下面的电路。应用这样的顶部包封材料可能涉及例如将光阻(例如不透明的)材料滴涂或注射到元件顶部表面的光感区域上。
这种方式可能显现多种缺陷或限制，包括例如：
-在顶部包封材料中的不期望的移动(shift)；
-待保护的光敏电路区域的不完全覆盖；
-由于缺乏标刻区域相对于周围透明区域的对比度而产生的标刻辨别困难。
图1和图2是包括例如芯片(或裸片)的电路12的电子元件10的示例图。专用集成电路或ASIC可以是这样电路的一个示例。
在一个或多个实施例中，元件可包括封装14(例如模制原料或MC)。
在一个或多个实施例中，封装14可包括“光透”材料，即对在可见光、IR和/或UV范围内的电磁辐射是透明的材料。
这样的“透明”封装材料可包括例如光硅树脂封装剂或透明转移模制原料。
在一个或多个实施例中，如图2中12a示意性地表示，电路(例如ASIC)12可通过不同途径(如焊接材料、胶或芯片粘接带(薄膜))被布置在裸片焊盘16上。
在一个或多个实施例中，裸片焊盘16可被放置在封装14的底表面上。在一个或多个实施例中可以不提供裸片焊盘16。
另外，在一个或多个实施例，元件10可包括单个电路12。在如图中所示例的一个或多个实施例中，元件10可包括其他元件，如具有电路12可操作地连接其上的MEMS 120，可提供相关联的处理功能。
元件(如元件10)的制作工艺可涉及，例如，将裸片12(如ASIC)安装到焊盘16上，用电导线22将裸片焊盘18安装到封装的引脚20，电导线22将焊盘18连接到引脚20，其可形成所谓的引线框。
如本文示例地，元件10可以随后被安装在基底上，例如印刷电路板或PCB(在图中不可见)上。裸片(如ASIC)12至“外部环境”的连接可以由顶部金属和底部金属层之间的引线接合和基底路由获得，其可由例如印刷电路板(PCB)、引线框或其他封装材料提供。
之前讨论的制造步骤可根据传统原理和规则进行，因而这里不必提供更多的细节描述。
至少理论上，一种存在的可能是提供元件10的“底边”激光标刻。
这可以在例如裸片焊盘16上，因而避免干扰封装(例如具有清澈/透明的顶层)和设备光学性能。
另外，在将元件10安装到例如PCB的基底上之前，一种可能的存在是，例如在用户侧，在该基底的特定区域(例如所谓的接触面积或安装PCB上的合模面)应用激光标刻。
这些布置将具有特定的固有缺陷：例如在元件10下面被“掩膜”将不可避免地结束标刻，一旦它被安装到例如PCB的基底上。
另外，这样的布置将无法为电路12的提供对环境光(可见光、IR和/或UV)的防护。
如所描述的，电路12可被具有光阻属性的所谓的“顶部包封”材料的涂层所覆盖。
可能除此之外，这种布置的缺点可能在于例如顶部包封材料不会被用于激光标刻。
在一个或多个实施例中，例如不透光半导体或金属的光阻层这样的盖状部件24可代替电路(如ASIC)12顶部上的这种顶部包封材料。
如这里所采用的，盖状部件将表示任何(小的)应用在电路12上并适于提供用于激光标刻的“平台”的材料平板，同时还可能为电路12的至少一部分形成光阻保护罩。
在一个或多个实施例中，盖状部件24可包括半导体材料的“裸”盖或板，半导体材料例如硅或如铜或铝这些具有良好氧化属性的金属。
在一个或多个实施例中，通过采用粘贴工艺(例如裸片粘贴工艺)，盖状部件24可被附着在电路12的顶边(即前表面)。引线上薄膜(FOW)技术可以是这种工艺的示例。
这样的盖状部件24既可提供辐射(可见光、IR和UV)阻隔属性还可提供用于激光标刻形成标刻平台。
图3的功能流程图是在一个或多个实施例中一系列步骤的示例。
在图3的流程图中，方框100表示不同步骤(已经已知)的完成，其引起完成元件10的全部内部封装组装，一直到盖状部件24(例如裸硅片)被布置到电路12的顶部的阶段。
在一个或多个实施例中，这可能涉及将盖状部件24安装(以及可能地切割)到FOW带26上，从而盖状部件24被裸片粘贴到电路12的线路结合连接22上。
在步骤102，激光标刻可发生以如所期望地在盖状部件24的顶部标记数据(追踪能力、厂商ID和车间ID等)。
这样的标刻M可包括字母(例如如图1中示例的ABS)、数字、符号或任意标记，它们被在图3流程中的步骤102所应用。
在一个或多个实施例中，元件10的制作过程可继续到封装14到元件的其他部分上的模制步骤104。
封装14可包括对可见光、IR和/或UV辐射透光(透明)的任意材料：对这种辐射的阻隔操作实际上是由盖状部件24实现的。
另外，在一个或多个实施例中，激光标刻到光阻盖状部件24上的标刻M将通过透光封装14而可见。
随后的步骤(例如PMC处理、切割等)可如方框106一般性表示的那样接着进行。
在一个或多个实施例中，具有应用在“平台”24上的标刻M的元件10还展现了所期望的电路12的光敏部分的保护性和光阻特性：应理解的是，平台24的保护效果实际上受到元件10的某些光/IR/UV敏感部分的限制。
一个或多个实施例可能的优点可包括以下：
通过使用应用在裸片粘贴工艺中的例如盖状部件24，标刻平台的提供可引起更保形的工艺，其在保形涂层重复性、产量、设备性能和UPH方面更稳定。
可用的标刻区域可被明显提升。例如，在一个1.0x 0.95mm的底部标刻区域的元件10中，可达到2.1x 1.3mm的顶部标刻区域(平台24)。
在一个或多个实施例中，这使得从受限标刻能力(例如三个字符)到可能大幅地应用超过三个字符的数据矩阵成为可能。
另外，半导体平台24的顶边标刻能力使得即便在元件10被安装到例如PCB上时标刻仍然能被读。
如图3中示例的工艺步骤使得在组装(步骤100)后而不是在裸片粘贴之前应用标刻(步骤102)成为可能，从而元件可承载与特定组装工艺更相关的数据。
一个或多个实施例可提供通过自动标准扫描设备裸眼可辨别的标刻(可能在封装模制，图3中步骤104之后)。
申请人进行的测试表明，实施例在热老化工艺的范围内不会影响电路12的性能，发现所谓的调和折衷小于基准功能测试器引入的误差。
在不损害基本原则的情况下，相对于以示例方式描述的内容，只要不脱离保护范围，细节和实施例可以改变，甚至显著地改变。
保护范围由所附权利要求确定。

Claims (2)

1.一种电子元件(10)，其特征在于，包括：
-至少一个电路(12)，具有前表面，以及位于所述至少一个电路(12)上的透光封装(14)；
-光阻材料的盖状部件(24)，应用在所述前表面上；以及
-所述元件(10)的标刻(M)，所述标刻被激光标刻(102)到所述光阻盖状部件(24)上，其中所述标刻(M)通过所述透光封装(14)可见。
2.根据权利要求1所述的电子元件，其特征在于，所述光阻盖状部件(24)包括半导体材料或金属材料。
CN201520967467.3U 2015-06-16 2015-11-27 电子元件 Expired - Fee Related CN205542766U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT102015000024379 2015-06-16
ITUB20151411 2015-06-16

Publications (1)

Publication Number Publication Date
CN205542766U true CN205542766U (zh) 2016-08-31

Family

ID=55273317

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201520967467.3U Expired - Fee Related CN205542766U (zh) 2015-06-16 2015-11-27 电子元件
CN201510850231.6A Pending CN106257665A (zh) 2015-06-16 2015-11-27 制作电子元件的方法及相应的电子元件

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201510850231.6A Pending CN106257665A (zh) 2015-06-16 2015-11-27 制作电子元件的方法及相应的电子元件

Country Status (2)

Country Link
US (1) US20160368098A1 (zh)
CN (2) CN205542766U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106257665A (zh) * 2015-06-16 2016-12-28 意法半导体(马耳他)有限公司 制作电子元件的方法及相应的电子元件

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134660A (ja) * 2000-10-26 2002-05-10 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6984876B2 (en) * 2004-05-27 2006-01-10 Semiconductor Components Industries, L.L.C. Semiconductor device formed having a metal layer for conducting the device current and for high contrast marking and method thereof
JP2006351772A (ja) * 2005-06-15 2006-12-28 Fujifilm Holdings Corp 半導体チップの識別情報記録方法及び撮像装置
US7675180B1 (en) * 2006-02-17 2010-03-09 Amkor Technology, Inc. Stacked electronic component package having film-on-wire spacer
US7615404B2 (en) * 2006-10-31 2009-11-10 Intel Corporation High-contrast laser mark on substrate surfaces
US8310069B2 (en) * 2007-10-05 2012-11-13 Texas Instruements Incorporated Semiconductor package having marking layer
US8582317B2 (en) * 2010-05-26 2013-11-12 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure therefor
KR100986664B1 (ko) * 2010-07-05 2010-10-11 이충해 교류용 발광 다이오드 발광 장치
WO2014129351A1 (ja) * 2013-02-21 2014-08-28 ピーエスフォー ルクスコ エスエイアールエル 半導体装置とその製造方法
ITTO20130967A1 (it) * 2013-11-28 2015-05-29 Stmicroelectronics Malta Ltd Metodo di impilamento di una pluralita' di piastrine per formare un dispositivo a semiconduttore impilato, e dispositivo a semiconduttore impilato
CN205542766U (zh) * 2015-06-16 2016-08-31 意法半导体(马耳他)有限公司 电子元件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106257665A (zh) * 2015-06-16 2016-12-28 意法半导体(马耳他)有限公司 制作电子元件的方法及相应的电子元件

Also Published As

Publication number Publication date
US20160368098A1 (en) 2016-12-22
CN106257665A (zh) 2016-12-28

Similar Documents

Publication Publication Date Title
TWI653736B (zh) 半導體封裝裝置及製造半導體封裝裝置之方法
JPH06503683A (ja) 光学電子装置構成要素パッケージ及び該パッケージを製造する方法
JPH09129780A (ja) Ｉｃパッケージ、光センサｉｃパッケージおよびこれらの組立方法
US20090051027A1 (en) Method of Manufacture and Identification of Semiconductor Chip Marked For Identification with Internal Marking Indicia and Protection Thereof by Non-black Layer and Device Produced Thereby
US11239176B2 (en) Package comprising identifier on and/or in carrier
US11901250B2 (en) Method of manufacturing semiconductor devices and corresponding device
TW200950017A (en) Sensing apparatus with packaging material as sensing protection layer and method of manufacturing the same
CN205542766U (zh) 电子元件
JP2009141147A (ja) 半導体装置の製造方法
CN105336629A (zh) 电子封装模块的制造方法以及电子封装模块
CN103247580A (zh) 电子器件模块以及制造方法
CN106469686B (zh) 半导体装置
JP5885342B2 (ja) 電子部品モジュールおよびその製造方法
JP3824742B2 (ja) 電子回路のパッケージ構造
JP2005317878A (ja) フォトリフレクタ装置及びその製造方法
JP4937581B2 (ja) 電子装置
US20080081407A1 (en) Protective coating for mark preservation
JP6317956B2 (ja) 圧力センサ、及び圧力センサの製造方法
CN110473790A (zh) 集成电路封装方法及半导体器件
CN107275228B (zh) 改善上盖板精度的半导体封装方法
CN217062093U (zh) SiP封装模组
KR100542667B1 (ko) 반도체패키지용 회로기판 및 캐리어프레임과 이를 이용한불량 회로기판의 감지 방법
US20220384211A1 (en) Method of manufacturing semiconductor devices and corresponding semiconductor device
TW201804580A (zh) 封裝體用基板、其製造方法以及封裝體
JP2001127236A (ja) Ｉｃパッケージ

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160831

Termination date: 20191127