ITTO20130967A1 - Metodo di impilamento di una pluralita' di piastrine per formare un dispositivo a semiconduttore impilato, e dispositivo a semiconduttore impilato - Google Patents

Metodo di impilamento di una pluralita' di piastrine per formare un dispositivo a semiconduttore impilato, e dispositivo a semiconduttore impilato

Info

Publication number
ITTO20130967A1
ITTO20130967A1 IT000967A ITTO20130967A ITTO20130967A1 IT TO20130967 A1 ITTO20130967 A1 IT TO20130967A1 IT 000967 A IT000967 A IT 000967A IT TO20130967 A ITTO20130967 A IT TO20130967A IT TO20130967 A1 ITTO20130967 A1 IT TO20130967A1
Authority
IT
Italy
Prior art keywords
semiconductor device
stacked semiconductor
stacking
plates
stacked
Prior art date
Application number
IT000967A
Other languages
English (en)
Inventor
Conrad Cachia
Kenneth Fonk
Original Assignee
Stmicroelectronics Malta Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stmicroelectronics Malta Ltd filed Critical Stmicroelectronics Malta Ltd
Priority to IT000967A priority Critical patent/ITTO20130967A1/it
Priority to US14/554,473 priority patent/US9290377B2/en
Publication of ITTO20130967A1 publication Critical patent/ITTO20130967A1/it

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0074—3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
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IT000967A 2013-11-28 2013-11-28 Metodo di impilamento di una pluralita' di piastrine per formare un dispositivo a semiconduttore impilato, e dispositivo a semiconduttore impilato ITTO20130967A1 (it)

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US14/554,473 US9290377B2 (en) 2013-11-28 2014-11-26 Method of stacking a plurality of dies to form a stacked semiconductor device, and stacked semiconductor device

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