CN202205747U - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN202205747U
CN202205747U CN2011203206489U CN201120320648U CN202205747U CN 202205747 U CN202205747 U CN 202205747U CN 2011203206489 U CN2011203206489 U CN 2011203206489U CN 201120320648 U CN201120320648 U CN 201120320648U CN 202205747 U CN202205747 U CN 202205747U
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mosfet
schottky diode
semiconductor device
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李铁生
张磊
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本实用新型公开了一种半导体器件，单片集成了金属氧化物半导体场效应晶体管(MOSFET)和肖特基二极管(Schottky diode)。该半导体器件包括：MOSFET区，包括MOSFET的有源区；肖特基二极管区，包括肖特基二极管的有源区；以及端接区，包括多个场限环结构，其中肖特基二极管区位于MOSFET区和端接区之间。根据本实用新型的半导体器件，可节省芯片的面积，提高开关速度并降低功率损耗。

Description

半导体器件
技术领域
本实用新型涉及半导体器件。
背景技术
金属半导体场效应晶体管(MOSFET)作为开关被广泛应用于直流/直流电源系统中。图1所示的降压(BUCK)电路中，为了防止开关管M1和M2切换时输入回路的短路直通，必须有一个死区时间。在该死区时间内，上管M1和下管M2均不导通，负载电阻RL上的输出电流通过下管M2的体二极管D0续流。由于PN结的导通压降比较大，约为0.7V，因此体二极管D0在正向导通时的功率损耗较大。此外，由于PN结中空穴和电子均参与导电，体二极管D0的反向恢复特性较差。
肖特基二极管具有不同于PN结的金属-半导体接触结构，即肖特基接触结构，使得肖特基二极管具有比PN结二极管小的正向压降，因而其导通损耗也较小。此外，肖特基二极管还具有良好的反向恢复特性，其反向恢复时间比PN结二极管短。
综上所述，可以将MOSFET与肖特基二极管集成于一个半导体器件中，利用肖特基二极管来实现MOSFET体二极管的作用。
实用新型内容
本实用新型的目的是提供一种单片集成金属半导体场效应晶体管(MOSFET)和肖特基二极管的半导体器件。
根据本实用新型实施例的一种半导体器件，其特征在于，包括：衬底；MOSFET区，形成于衬底上，包括MOSFET的有源区；肖特基二极管区，形成于衬底上，包括肖特基二极管的有源区；以及端接区，形成于衬底上，包括多个场限环结构；其中肖特基二极管区位于MOSFET区与端接区之间。
在一个实施例中，肖特基二极管的阳极电耦接至MOSFET的源极，肖特基二极管的阴极电耦接至MOSFET的漏极。
在一个实施例中，肖特基二极管区环绕MOSFET区。
在一个实施例中，所述半导体器件进一步包括：源极金属层，位于MOSFET区和肖特基二极管区的上方，以及与衬底的掺杂类型不同的多个环状掺杂区，形成于衬底上，位于肖特基二极管区内并环绕MOSFET区。
在一个实施例中，所述多个环状掺杂区处于源极金属层的外围区域下方。
在一个实施例中，所述源极金属层电耦接至MOSFET的源极、肖特基二极管的阳极以及多个环状掺杂区。
根据本实用新型实施例的一种半导体器件，其特征在于，包括：衬底，位于半导体器件的底部，具有第一掺杂类型；外延层，位于衬底的上方，具有第一掺杂类型；MOSFET，包括体区、源极区、漏极区和栅极区，其中体区与源极区位于外延层内；多个环状掺杂区，具有第二掺杂类型，位于外延层内并环绕MOSFET；多个肖特基接触，位于多个环状掺杂区之间；以及源极金属层，位于MOSFET与肖特基接触的上方。
在一个实施例中，所述源极金属层电耦接至源极区、肖特基接触以及多个环状掺杂区。
在一个实施例中，所述半导体器件进一步包括：栅极金属层，位于多个环状掺杂区之外，其中多个环状掺杂区与栅极金属层被多个场限环结构环绕。
在一个实施例中，所述第一掺杂类型为N型，第二掺杂类型为P型。
通过将MOSFET与肖特基二极管集成于一个半导体器件中，利用肖特基二极管来实现MOSFET体二极管的作用，可节省芯片的面积，提高开关速度并降低功率损耗。
附图说明
为了更好地理解本实用新型，将根据以下附图对本实用新型进行详细描述：
图1是现有的BUCK电路；
图2A是根据本实用新型一实施例的集成MOSFET和肖特基二极管的半导体器件的示意图；
图2B是根据本实用新型一实施例的形成于图2A所示半导体器件上电路的电路图；
图3是根据本实用新型一实施例的集成MOSFET与肖特基二极管的半导体器件的布局图；
图4是根据本实用新型一实施例的集成槽栅型MOSFET与肖特基二极管的图3所示半导体器件的A-A剖视图；
图5是根据本实用新型另一实施例的集成常规MOSFET与肖特基二极管的图3所示半导体器件的A-A剖视图。
具体实施方式
下面参照附图更充分地描述本实用新型的示范实施例。然而，本实用新型可以以许多不同形式体现，不应理解为局限于这里阐述的示范实施方式，而是提供这些示例使得本实用新型公开的充分和全面。
附图是示范实施例方式和/或中间结构的理想示意图。应理解，例如制造技术和/或容差导致的图示形状的变化是可以预期的。因此，本实用新型的示范实施例方式不应解释为局限于这里所示区域的特定方式，还应该包括例如制造工艺导致的形状偏差。因此，图中显示的区域实质上是示意性的，它们的形状不意图限定本实用新型的范围。还应理解，附图不是按比例画的，为了清晰，层和区域的尺寸可被放大。
在本说明书中，用“+”和“-”来描述掺杂区的相对浓度，但是这并不限制掺杂区的浓度范围，也不对掺杂区进行其他方面的限制。例如，下面描述为N+或N-的掺杂区，亦可以称为N型掺杂区。此外，本文所称“耦接”的含义为直接连接，或通过其他导体，例如金属，间接连接。
图2A是根据本实用新型一实施例的集成MOSFET和肖特基二极管的半导体器件的示意图。该半导体器件200包括形成于同一衬底上的MOSFET区21、肖特基二极管区22以及端接区(termination area)23。MOSFET区21包括MOSFET的有源区。肖特基二极管区22位于MOSFET区21和端接区23之间，包括肖特基二极管的有源区。在一个实施例中，肖特基二极管区22环绕MOSFET区21。在一个实施例中，端接区23包括多个场限环结构。在一个实施例中，端接区23进一步包括栅极金属层。
图2B所示为根据本实用新型一实施例的形成于图2A所示半导体器件200上的电路200B的电路图。电路200B包括：集成于同一半导体衬底上的MOSFET管M和肖特基二极管D1，该肖特基二极管D1与MOSFET管M的体二极管D0并联。如图2B所示，MOSFET管M形成于MOSFET区21中，肖特基二极管D1形成于肖特基二极管区22中。肖特基二极管D1具有阳极和阴极，MOSFET管M具有源极S、栅极G和漏极D。肖特基二极管D1的阳极电耦接至MOSFET管的源极S，阴极电耦接至MOSFET管的漏极D。在一个实施例中，电路200B可用作BUCK电路的下管。由于肖特基二极管D1的正向压降比体二极管D0小，在死区时间内电流将流过肖特基二极管D1。当MOSFET管的漏极电位高于源极电位时，肖特基二极管D1的反向恢复时间比体二极管D0短。因而电路200B可实现比单个MOSFET更快的开关速度和更小的功率损耗。
由于肖特基二极管区22环绕MOSFET区21的外围，半导体器件200的尺寸利用率高。而且，由于流过肖特基二极管的正向电流分散而非集中于一处，可在不影响半导体器件200击穿电压的前提下，得到更好的热特性。
图3是根据本实用新型一实施例的集成MOSFET与肖特基二极管的半导体器件300的布局图。图3中用虚线框1、2、3将半导体器件300划分为三个区域。虚线框1内的区域为MOSFET区31；虚线框1以外、虚线框2以内的区域为肖特基二极管区32；虚线框2以外、虚线框3以内的区域为端接区33。在一个实施例中，半导体器件300还包括位于肖特基二极管区32与端接区33之间的其他电路和/或结构。在一个实施例中，MOSFET区31、肖特基二极管区32和端接区33可能仅是半导体器件300的一部分，或者说，半导体器件300还包括位于虚线框3以外的其它电路和/或结构。
如图3所示，斜线填充的环状掺杂区301形成于半导体器件300的衬底上，位于肖特基二极管区32内并环绕MOSFET区31，其掺杂类型与半导体器件300衬底的掺杂类型不同。在肖特基二极管区32中的任意两个环状掺杂区之间，制作肖特基接触以形成肖特基二极管。半导体器件300的衬底为第一掺杂类型，环状掺杂区301为第二掺杂类型。在一种实施例中，半导体器件300中的MOSFET是NMOS，衬底为N掺杂类型，环状掺杂区301为P掺杂类型。
在一个实施例中，端接区33包括多个与衬底掺杂类型不同的场限环结构。尽管图3中肖特基二极管区32和端接区33中分别仅画出两个环状掺杂区和两个场限环结构，实际上它们的数目可能不止两个。在一个实施例中，环状掺杂区301的形状可能与图3所示的有所不同。例如，肖特基二极管区32中的环状掺杂区301可以是断续的。
点状填充区302用来表示金属布图区。位于MOSFET区31和肖特基二极管区32之上的金属布图区为源极金属层，在虚线框2右下方的矩形金属布图区为栅极金属层。在一个实施例中，肖特基二极管区32中的环状掺杂区处于源极金属层的外围区域下方。在一个实施例中，源极金属层电耦接至MOSFET的源极、肖特基二极管的阳极和肖特基二极管区32中的多个环状掺杂区。栅极金属层连接至MOSFET的栅极。如图3所示，栅极金属层位于端接区33内、肖特基二极管区32中的环状掺杂区之外。在一个实施例中，栅极金属层与肖特基二极管区32中的环状掺杂区被端接区33中的多个场限环结构所包围。
图4是根据本实用新型一实施例的集成槽栅型MOSFET与肖特基二极管的图3所示半导体器件300的A-A剖视图400。图4仅给出图3所示半导体器件300中沿A-A切断线的这部分剖视图，而非全部。
如图4所示，半导体器件400包括MOSFET区41、肖特基二极管区42和端接区43。形成于MOSFET区41中的MOSFET和形成于肖特基二极管区42中的肖特基二极管均为N型垂直导电器件。在另一实施例中，PMOS与P型肖特基二极管被集成于同一半导体衬底上，其中各区的掺杂类型与图4所示的掺杂类型相反。
如图4所示，位于半导体器件底部的N+型衬底401、位于N+型衬底401上的N-型外延层402以及位于顶部的绝缘层403是共用的，也就是说，MOSFET区41、肖特基二极管区42和端接区43共用衬底401、外延层402以及绝缘层403。N+型衬底401作为MOSFET的漏极和肖特基二极管的阴极。在一种实施例中，N-层402为衬底，而N+层401为外延层。在另一实施例中，层401与402都为衬底的一部分。
槽栅型MOSFET形成于MOSFET区41中，包括用作漏极区的N+型衬底401、用作体区的P型掺杂区412、用作源极区的N+型掺杂区414和用作栅极区的槽栅区415。体区412与源极区414位于N-型外延层402内。在一个实施例中，槽栅型MOSFET还包括P+型体接触区413、源极接触411以及位于槽栅区外沿的栅介质层416。P+型体接触区413通过源极接触411耦接至作为MOSFET源极S的源极金属层40。在一个实施例中，槽栅区415中填充多晶硅材料。
在肖特基二极管区42中，多个环状P型掺杂区422形成于外延层内并环绕MOSFET区41，用于提高肖特基二极管的击穿电压。肖特基接触421位于该多个环状掺杂区422之间。源极金属层40位于MOSFET区和肖特基二极管区42之上，电耦接至MOSFET的源极区414、肖特基接触421和环状P型掺杂区422。
端接区43中的P型掺杂区432用作场限环结构。位于N-型外延层402中的P型掺杂区412、422与432可共用同一层掩膜。在一个实施例中，半导体器件400还进一步包括绝缘层403，用于电气隔离。
当MOSFET导通时，电流流经位于槽栅区415附近的沟道。当MOSFET关断时，电流主要流经导通电阻较小的肖特基二极管。此时，电流依次流经源极金属层40(肖特基二极管的阳极)、肖特基接触421、N-型外延层402，最后到达N+型衬底401(肖特基二极管的阴极)。当MOSFET的漏极电位大于源极电位时，由于肖特基二极管是单载流子器件(仅电子)，因此其反向恢复时间很短。在一个实施例中，半导体器件400被用作整流管，既具有MOSFET的优点，又由于内部集成肖特基二极管的缘故，在死区期间内导通损耗小，反向恢复特性好。此外，由于环状P型掺杂区422电耦接至肖特基接触421，可以在漏源极电压VDS足够高时掐断位于其间的肖特基二极管区，防止肖特基二极管被击穿。
在一个实施例中，肖特基二极管区42中的环状P型掺杂区422、P+型接触区423、金属接触424分别与MOSFET区中的P型体区412、P+型体接触区413、源极区414共用一层掩膜。在一个实施例中，肖特基接触421与MOSFET的源极接触411共用一层掩膜，这样使得在将肖特基二极管与MOSFET集成时，与单独集成MOSFET相比，无需使用更多层掩膜。
图5是根据本实用新型另一实施例的集成常规MOSFET与肖特基二极管的图3所示半导体器件的A-A剖视图。图5所示半导体器件的结构与图4所示结构类似，只是其中的MOSFET为传统的MOSFET。该MOSFET的栅极G为薄膜工艺制作而成，包括位于N-型外延层502之上的栅极区515和绝缘层516。在一个实施例中，栅极区515由多晶硅材料制作而成。
图3到图5所示的实施例中，多个环状掺杂区处于源极金属层的外围区域下方。肖特基二极管制作于这些环状P型掺杂区之间，并环绕MOSFET的有源区，因此提高了芯片尺寸利用率，使得半导体器件的尺寸更小。同时，由于肖特基二极管的正向导通电流分散而非集中于一处，使得半导体器件具有更好的热特性。此外，多个环状P型掺杂区不仅易于集成，而且可以进一步提高半导体器件的击穿电压。
本领域技术人员应该理解，MOSFET区与端接区，或者肖特基二极管区并不仅限于前面图中所描述的结构，本实用新型不限于这些实施例方式，在不脱离权利要求所限定的本实用新型的精神和范围内，本领域技术人员可以进行各种修改和变型等。

Claims (10)

1.一种半导体器件，其特征在于，包括：
衬底；
MOSFET区，形成于衬底上，包括MOSFET的有源区；
肖特基二极管区，形成于衬底上，包括肖特基二极管的有源区；以及
端接区，形成于衬底上，包括多个场限环结构；
其中肖特基二极管区位于MOSFET区与端接区之间。
2.如权利要求1所述的半导体器件，其特征在于，肖特基二极管的阳极电耦接至MOSFET的源极，肖特基二极管的阴极电耦接至MOSFET的漏极。
3.如权利要求1所述的半导体器件，其特征在于，肖特基二极管区环绕MOSFET区。
4.如权利要求1所述的半导体器件，其特征在于，进一步包括：
源极金属层，位于MOSFET区和肖特基二极管区的上方，以及
与衬底的掺杂类型不同的多个环状掺杂区，形成于衬底上，位于肖特基二极管区内并环绕MOSFET区。
5.如权利要求4所述的半导体器件，其特征在于，所述多个环状掺杂区处于源极金属层的外围区域下方。
6.如权利要求4所述的半导体器件，其特征在于，所述源极金属层电耦接至MOSFET的源极、肖特基二极管的阳极以及多个环状掺杂区。
7.一种半导体器件，其特征在于，包括：
衬底，位于半导体器件的底部，具有第一掺杂类型；
外延层，位于衬底的上方，具有第一掺杂类型；
MOSFET，包括体区、源极区、漏极区和栅极区，其中体区与源极区位于外延层内；
多个环状掺杂区，具有第二掺杂类型，位于外延层内并环绕MOSFET；
多个肖特基接触，位于多个环状掺杂区之间；以及
源极金属层，位于MOSFET与肖特基接触的上方。
8.如权利要求7所述的半导体器件，其特征在于，所述源极金属层电耦接至源极区、肖特基接触以及多个环状掺杂区。
9.如权利要求7所述的半导体器件，其特征在于，进一步包括：
栅极金属层，位于多个环状掺杂区之外，其中多个环状掺杂区与栅极金属层被多个场限环结构环绕。
10.如权利要求7所述的半导体器件，其特征在于，所述第一掺杂类型为N型，第二掺杂类型为P型。
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