CN106057798A - 一种集成沟槽肖特基的mosfet - Google Patents

一种集成沟槽肖特基的mosfet Download PDF

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CN106057798A
CN106057798A CN201610481044.XA CN201610481044A CN106057798A CN 106057798 A CN106057798 A CN 106057798A CN 201610481044 A CN201610481044 A CN 201610481044A CN 106057798 A CN106057798 A CN 106057798A
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doped region
mosfet
schottky
heavily doped
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CN106057798B (zh
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李泽宏
李爽
陈文梅
陈哲
曹晓峰
李家驹
罗蕾
任敏
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University of Electronic Science and Technology of China
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Abstract

本发明属于半导体技术，特别涉及一种集成沟槽肖特基的MOSFET。该集成沟槽肖特基的MOSFET为在MOSFET中集成有由肖特基接触与衬底形成的肖特基二极管，肖特基结由金属层与N型轻掺杂环接触形成，位于MOSFET槽型栅极下方，其肖特基二极管的阳极电位通过阳极引出金属与MOSFET的源极相连。本发明的肖特基二极管与MOSFET二极管的集成更为紧凑，位于体内的肖特基结减小了占用的芯片面积。

Description

一种集成沟槽肖特基的MOSFET
技术领域
本发明属于功率半导体领域，特别涉及一种集成沟槽肖特基的MOSFET。
背景技术
高性能转换器设计中的同步整流对于低电压、高电流应用至关重要，这是因为通过将肖特基整流替换为同步整流MOSFET能够显著提高效率和功率密度。在实际应用中，同步整流MOSFET的功率损耗主要由导通损耗、开关损耗以及体二极管导通损耗等组成。例如，在DC-DC转换电路中，低边的功率开关的功率损耗中，体二极管的导通损耗仍然影响MOSFET的总体损耗。随着功率开关应用中高频和大电流的要求的提高，降低功率损耗的需求受到了越来越多的重视。
为了降低功率MOSFET体二极管的功率损耗，采用MOSFET与肖特基二极管并联的方式，由于肖特基二极管的正向开启电压(约为0.35V)比PN结二极管的内建电势(约0.7V)小，因此减少体二极管正向开启电压，减小体二极管死区损耗。
集成MOSFET与肖特基二极管虽然解决了体二极管导通时开启电压过高的问题，但是传统的集成方式导致了需要较大的芯片面积，尤其是在承受较高电流的时候。美国6987305B2号专利“Intergrated FET and schottky device”公开过几种不同的肖特基与MOSFET集成的结构与制作方法，提出了紧密的肖特基与MOSFET集合装置，减小了损耗，然而这些装置中的平面肖特基区域仍需占用较大的芯片面积。
发明内容
本发明的目的，就是为了解决肖特基结集成在MOSFET中占用芯片面积的问题，提出了一种集成沟槽肖特基的MOSFET。
本发明的技术方案：一种集成沟槽肖特基的MOSFET，包括从下至上依次层叠设置的漏极金属层12、N型重掺杂衬底1、N型漂移区2、P型掺杂区3和源极金属层10；所述P型掺杂区3中具有N型重掺杂区5、P型重掺杂区4和沟槽9，所述N型重掺杂区5位于P型掺杂区3的上层，N型重掺杂区5的上表面与源极金属层10接触，所述沟槽9贯穿N型重掺杂区5的中部并向下延伸至N型漂移区2中，沟槽9的上表面与源极金属层10接触；所述P型重掺杂区4位于N型重掺杂区5远离沟槽9的一侧，P型重掺杂区4与N型重掺杂区5的底部连接，形成欧姆接触；源极金属层10沿N型重掺杂区5的侧面向下延伸至与P型重掺杂区4接触；所述沟槽9中填充有介质6，在介质6中具有多晶硅7；所述沟槽9位于N型漂移区2中部分的末端填充有金属8；所述N型漂移区2中还具有N型轻掺杂环11，所述N型轻掺杂环11与金属8接触，并形成肖特基结；所述金属8与源极金属层10电气连接；所述多晶硅7为栅电极；所述P型掺杂区3的掺杂浓度大于N型漂移区2的掺杂浓度两个数量级；所述的P型重掺杂区4的掺杂浓度大于P型掺杂区3的掺杂浓度两到三个数量级。
进一步的，所述沟槽9下方两侧具有P型浮空岛14。
本发明所提供的一种紧密的集成沟槽肖特基的MOSFET，为在MOSFET中并联肖特基二极管。如图1所示，为所述一种紧密的集成沟槽肖特基的MOSFET的剖面图，所述肖特基二极管的阳极设置在MOSFET元胞区域的槽型栅下方，由阳极和漂移区形成肖特基接触；如图2所示，为所述一种紧密的集成沟槽肖特基的MOSFET的三维结构图，图中示出了肖特基二极管的阳极与MOSFET的源端相连，通过阳极引出金属13，与位于表面的源极金属相连；如图3所示，为图2中三维结构沿z方向的剖面示意图。图3中示出阳极引出金属13周围填充介质层6，与P型掺杂区3及N型重掺杂区5隔离，但与金属层8相连。位于肖特基二极管的阴极共用位于衬底背面的漏电极所述MOSFET的源极作为肖特基二极管的阳极，所述MOSFET背面的漏极作为肖特基二极管的阴极。图4中示出了本发明的一种紧密的集成沟槽肖特基的MOSFET的版图示意例图1，MOSFET结构为条形元胞，方向与x轴坐标平行，阳极引出区垂直于条形元胞方向，方向与Y轴坐标平行。US6987305B2号专利“Intergrated FET and schottky device”中肖特基二极管的肖特基结在芯片表面，占据较大的芯片面积，本发明提出的紧密的集成沟槽肖特基MOSFET可根据不同的版图设计，仅在芯片表面占据一部分阳极引出区域，其宽度为栅极线宽，占用芯片面积非常小。图5中示出了一种紧密的集成沟槽肖特基的MOSFET的版图示意例图2，相较于版图示意例图1，阳极引出区域的占用面积更小。
本发明的工作原理为：栅极电压达到阈值电压时，MOSFET正向导通。位于阳极引出金属13两侧的P型掺杂区3在MOSFET导通时不会形成反型层，因此，阳极引出金属13两侧没有电流通路。此时，位于阳极引出金属13两侧的N型重掺杂区5中的电子通过位于栅极两侧的路径流出。此时，肖特基二极管的阳极相对于阴极接低电位，肖特基结反偏，肖特基二极管处于反向阻断状态。N-型保护环11使得肖特基二极管的耐压增大，但同时增加了肖特基二极管的开启电压。
栅极电位在未达到阈值电压时，MOSFET不能导通，此时，肖特基二极管较MOSFET体二极管先导通。电子越过势垒从半导体中进入金属界面，不发生积累直接流走。
综上所述，本发明的有益效果为：一种集成沟槽肖特基的MOSFET，肖特基结由金属层8与N型轻掺杂环11接触形成，位于MOSFET槽型栅极7下方，其肖特基二极管的阳极电位通过阳极引出金属13与MOSFET的源极相连。本发明的肖特基二极管与MOSFET二极管的集成更为紧凑，位于体内的肖特基结减小了占用的芯片面积。
附图说明
图1是实施例1所提供的一种紧密的集成沟槽肖特基的MOSFET的剖面结构；
图2是实施例1所提供的一种紧密的集成沟槽肖特基的MOSFET的三维结构图；
图3是实施例1所提供的一种紧密的集成沟槽肖特基的MOSFET的沿图2中三维结构图z方向的剖面图；
图4是实施例1所提供的一种紧密的集成沟槽肖特基的MOSFET的版图示意例图1；
图5是实施例1所提供的一种紧密的集成沟槽肖特基的MOSFET的版图示意例图2；
图6是实施例2所提供的一种紧密的集成沟槽肖特基的MOSFET的剖面结构。
具体实施方式
下面结合附图和实施例，详细描述本发明的技术方案：
本发明所提供的一种集成沟槽肖特基的MOSFET，为在MOSFET中并联肖特基二极管。如图1所示，为所述一种紧密的集成沟槽肖特基的MOSFET的剖面图，所述肖特基二极管的阳极设置在MOSFET元胞区域的槽型栅下方，由阳极和漂移区形成肖特基接触；如图2所示，为所述一种紧密的集成沟槽肖特基的MOSFET的三维结构图，图中示出了肖特基二极管的阳极与MOSFET的源端相连，通过阳极引出金属13，与位于表面的源极金属相连；如图3所示，为图2中三维结构沿z方向的剖面示意图。图3中示出阳极引出金属13周围填充介质层6，与P型掺杂区3及N型重掺杂区5隔离，但与金属层8相连。位于肖特基二极管的阴极共用位于衬底背面的漏电极所述MOSFET的源极作为肖特基二极管的阳极，所述MOSFET背面的漏极作为肖特基二极管的阴极。图4中示出了本发明的一种集成沟槽肖特基的MOSFET的版图示意例图1，MOSFET结构为条形元胞，方向与x轴坐标平行，阳极引出区垂直于条形元胞方向，方向与Y轴坐标平行。US6987305B2号专利“Intergrated FET and schottky device”中肖特基二极管的肖特基结在芯片表面，占据较大的芯片面积，本发明提出的集成沟槽肖特基MOSFET可根据不同的版图设计，仅在芯片表面占据一部分阳极引出区域，其宽度为栅极线宽，占用芯片面积非常小。图5中示出了一种集成沟槽肖特基的MOSFET的版图示意例图2，相较于版图示意例图1，阳极引出区域的占用面积更小。
实施例1
如图1所示，本例包括从下至上依次层叠设置的漏极金属层12、N型重掺杂衬底1、N型漂移区2、P型掺杂区3和源极金属层10；所述P型掺杂区3中具有N型重掺杂区5、P型重掺杂区4和沟槽9，所述N型重掺杂区5位于P型掺杂区3的上层，N型重掺杂区5的上表面与源极金属层10接触，所述沟槽9贯穿N型重掺杂区5的中部并向下延伸至N型漂移区2中，沟槽9的上表面与源极金属层10接触；所述P型重掺杂区4位于N型重掺杂区5远离沟槽9的一侧，P型重掺杂区4与N型重掺杂区5的底部连接，形成欧姆接触；源极金属层10沿N型重掺杂区5的侧面向下延伸至与P型重掺杂区4接触；所述沟槽9中填充有介质6，在介质6中具有多晶硅7；所述沟槽9位于N型漂移区2中部分的末端填充有金属8；所述N型漂移区2中还具有N型轻掺杂环11，所述N型轻掺杂环11与金属8接触，并形成肖特基结；所述金属8与源极金属层10电气连接；所述多晶硅7为栅电极；所述P型掺杂区3的掺杂浓度大于N型漂移区2的掺杂浓度两个数量级；所述的P型重掺杂区4的掺杂浓度大于P型掺杂区3的掺杂浓度两到三个数量级。
本例的工作原理为：
栅极电压达到阈值电压时，MOSFET正向导通。位于阳极引出金属13两侧的P型掺杂区3在MOSFET导通时不会形成反型层，因此，阳极引出金属13两侧没有电流通路。此时，位于阳极引出金属13两侧的N型重掺杂区5中的电子通过位于栅极两侧的路径流出。此时，肖特基二极管的阳极相对于阴极接低电位，肖特基结反偏，肖特基二极管处于反向阻断状态。N-型保护环11使得肖特基二极管的耐压增大，但同时增加了肖特基二极管的开启电压。
栅极电位在未达到阈值电压时，MOSFET不能导通，此时，肖特基二极管较MOSFET体二极管先导通。电子越过势垒从半导体中进入金属界面，不发生积累直接流走。
实施例2
本例在实施例1的基础上，去掉N-型保护环11，在槽9两侧有P型浮空岛14，在肖特基二极管反偏时与N型漂移区形成耗尽层，防护肖特基结击穿，减小漏电流。同时进一步的减小了肖特基二极管的开启电压。
以实施例1为例，本发明结构可以用以下方法制备得到，工艺步骤为：
1、单晶硅准备。采用N型重掺杂单晶硅衬底1，晶向为<100>。
2、外延生长。采用气相外延VPE等方法生长一定厚度和掺杂浓度的N型外延层。
3、P型掺杂区3注入。光刻出P型掺杂区3的图形然后高能硼离子注入，注入角度可根据要求改变，通过调整注入能量和剂量改变掺杂浓度和结深。
4、N+源区的制备。砷注入制备N型重掺杂区5。
5、源极浅槽刻蚀，P型重掺杂注入，形成P型重掺杂区4。
6、槽9刻蚀。采用离子刻蚀等方法在N型外延层上刻蚀出一定深度和宽度的槽。
7、槽内金属淀积。在整个器件表面溅射一层金属铝，在槽9内填充金属，形成肖特基结，同时形成阳极引出金属13。
8、金属层8的形成。在整个芯片表面涂抹1μm厚的光刻胶，然后用光刻胶转移金属层8的版图到硅片表面，刻蚀掉暴露的金属，在槽9内保留一定厚度的金属形成金属层8，与N型漂移区接触形成肖特基结；
9、栅电极的制备。首先在整个硅片表面淀积氧化层，然后用光刻胶转移版图到硅片表面，刻蚀掉暴露的氧化层，保留槽9内的氧化层；接着淀积多晶硅，光刻、刻蚀形成栅电极7，最后，在表面继续淀积氧化层并进行机械磨平。
10、正面金属化阳极。在整个器件表面溅射一层金属铝，形成金属化阳极10。11、背面减薄、金属化，形成漏电极12。
制作器件时，还可用碳化硅、砷化镓或锗硅等半导体材料替代体硅。

Claims (2)

1.一种集成沟槽肖特基的MOSFET，包括从下至上依次层叠设置的漏极金属层(12)、N型重掺杂衬底(1)、N型漂移区(2)、P型掺杂区(3)和源极金属层(10)；所述P型掺杂区(3)中具有N型重掺杂区(5)、P型重掺杂区(4)和沟槽(9)，所述N型重掺杂区(5)位于P型掺杂区(3)的上层，N型重掺杂区(5)的上表面与源极金属层(10)接触，所述沟槽(9)贯穿N型重掺杂区(5)的中部并向下延伸至N型漂移区(2)中，沟槽(9)的上表面与源极金属层(10)接触；所述P型重掺杂区(4)位于N型重掺杂区(5)远离沟槽(9)的一侧，P型重掺杂区(4)与N型重掺杂区(5)的底部连接，形成欧姆接触；源极金属层(10)沿N型重掺杂区(5)的侧面向下延伸至与P型重掺杂区(4)接触；所述沟槽(9)中填充有介质(6)，在介质(6)中具有多晶硅(7)；所述沟槽(9)位于N型漂移区(2)中部分的末端填充有金属(8)；所述N型漂移区(2)中还具有N型轻掺杂环(11)，所述N型轻掺杂环(11)与金属(8)接触，并形成肖特基结；所述金属(8)与源极金属层(10)电气连接；所述多晶硅(7)为栅电极；所述P型掺杂区(3)的掺杂浓度大于N型漂移区(2)的掺杂浓度两个数量级；所述的P型重掺杂区(4)的掺杂浓度大于P型掺杂区(3)的掺杂浓度两到三个数量级。
2.根据权利要求1所述的一种集成沟槽肖特基的MOSFET，其特征在于，所述沟槽(9)下方两侧具有P型浮空岛(14)。
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