CN1934703A - 用于射频应用的单片集成电路 - Google Patents

用于射频应用的单片集成电路 Download PDF

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CN1934703A
CN1934703A CNA2004800398992A CN200480039899A CN1934703A CN 1934703 A CN1934703 A CN 1934703A CN A2004800398992 A CNA2004800398992 A CN A2004800398992A CN 200480039899 A CN200480039899 A CN 200480039899A CN 1934703 A CN1934703 A CN 1934703A
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T·阿恩博格
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Abstract

一种单片集成电路，尤其一种用于射频功率应用的集成电路，其包含：一晶体管(11；15)，优选地为一功率LDMOS晶体管；和一螺旋电感器(12；26；41；52，53)，优选地为一RF阻塞电感器。将所述螺旋电感器配置在所述晶体管的顶上，藉此所述螺旋电感器与所述晶体管之间的电磁耦合通常不可能避免。然而，所述晶体管具有一指型布图(13a至13k，14a至14f)以防止发生由所述电磁耦合导致的任何有效涡电流。通过此类配置大大减小了所述电路所需要的芯片面积。

Description

用于射频应用的单片集成电路
技术领域
本发明大体上涉及集成电路技术领域，且更确切地说，本发明涉及包含晶体管和螺旋电感器的单片集成电路。
背景技术
集成电感器已得以广泛用于RF(射频)功率应用的集成电路中。电感器通常定位在与例如晶体管的有源器件分离的区域中，以避免不必要的干扰现象。归因于由设计规则所强加的有限的可能几何结构，且归因于所要的Q和电感值，所述电感器会占用相当多的空间。这可导致体积庞大且因此减慢电路的速度。
发明内容
因此，本发明的目标在于提供一种包含晶体管和螺旋电感器的单片集成电路，尤其用于射频应用的集成电路，与现有技术解决方案所要求的芯片面积相比，所述单片集成电路使用更小的芯片面积。
因此，本发明的特殊目标在于提供这样一种电路，可对所述电路利用集成电路的新设计规则，这会导致所制造的器件的面积减少且速度可能增加。
根据本发明，通过如所附专利权利要求书中所主张的单片集成电路来达到这些目标。
通过提供一种包含晶体管和螺旋电感器且其中所述螺旋电感器配置在所述晶体管的顶上的单片集成电路，尤其用于射频应用的集成电路，节省了有价值的芯片面积。晶体管具有指型布图，以防止发生由螺旋电感器与晶体管之间的电磁耦合所导致的任何有效涡电流。
从下文给出的本发明的优选实施例的详细描述和附图1至5中，本发明的进一步特征及其优势将变得明显。本发明的优选实施例的详细描述和附图1-5仅以说明的方式给出，且因此不限制本发明。
附图说明
图1是根据本发明优选实施例的单片集成电路的高度放大示意布图图。
图2a是包含于图1的单片集成电路的晶体管中的晶体管单元的高度放大示意布图图。
图2b是图2a的晶体管单元沿着线A-A截取的的高度放大横截面图，其中展示包含于图1的单片集成电路中的钝化层和电感器的一部分。
图3是根据本发明进一步优选实施例的电路的电路图。
图4和图5的每一者均是根据本发明个别进一步优选实施例的单片集成电路的高度放大示意布图图。
具体实施方式
图1中示意展示根据本发明第一优选实施例的单片集成电路。所述电路尤其以RF应用为目标，其在半导体上包含晶体管11和配置在所述晶体管11的顶上的螺旋电感器12，所述半导体优选为硅，芯片衬底。在此实施例中，晶体管11为LDMOS功率晶体管，晶体管11具有指型布图且包含平行配置的若干栅极指状物13a至13f。类似地，若干导电漏极指状物14a至14c配置于所述栅极指状物13a至13f之间，以形成相互交叉结构。掺杂的细长漏极区域形成于衬底中且位于所述漏极指状物14a至14c中的每一者的下面。栅极指状物13a至13f经由在晶体管11的第一侧处的共栅连接(common gate connection)15而彼此连接，而漏极指状物14a至14c经由在晶体管11的大体上与所述第一侧相对的第二侧处的共漏连接16而彼此连接。LDMOS晶体管的源极连接在芯片衬底的底部或后侧。细长的掺杂源极区域形成于衬底中且在栅极指状物13b与13c之间和栅极指状物13d与13e之间，使得如从上方所见，漏极指状物/区域和源极区域交替地配置于每两个邻近的栅极指状物13a至13f之间。
可重复所述结构以形成LDMOS晶体管11，其与图1中所说明的晶体管相比，具有更多栅极与漏极指状物/区域和源极区域。
另外，LDMOS晶体管11可不连接在芯片衬底的后侧处，而是在源极区域中的每一者的顶上包含导电源极指状物，其中这些源极指状物连接在一起，与栅极指状物13a至13f或漏极指状物14a至14c连接在一起的方式类似。
借助于本发明，包括晶体管和电感器的电路所需要的芯片面积大大减小。如果晶体管的横向尺寸与电感器的横向尺寸类似，那么所需的芯片面积减为二分之一。面积节省当然取决于特定电路设计，但此对于晶体管和螺旋电感器的大小类似的功率放大器件且对于电路或芯片的主要部分而言非常常见。
单片集成电路优选地以例如标准BiCMOS或CMOS工艺的常规硅IC工艺来制造，且不需要使用既复杂又麻烦、或与常规IC处理不兼容、或包括过多数目的步骤的处理。通常在以此类工艺形成的一些金属化层中制成所述电感器。因此，晶体管11与电感器12之间的垂直距离通常对应于形成于晶体管与金属化层之间的钝化层的厚度。如果在一些上金属化层中制造电感器(此为优选的以避免直接短路且使与下面的晶体管的磁耦合最小化)，那么垂直间隔可能归因于下金属化层及其中间介电层的厚度而更大。晶体管11与电感器12之间的垂直距离优选地小于25微米，更优选地小于10微米，且最优选地小于几微米。
虽然图1的配置节省有价值的芯片面积，但两个器件之间的不必要的电磁耦合很难避免。晶体管11中最可能会感应到与螺旋电感器12中的电流类似但具有相对方向的环电流。
晶体管11的指型布图对防止由电磁耦合导致的任何有效环电流或涡电流流动来说很重要，有效环电流或涡电流对电路的操作而言是灾难性的。因此，虽然任意选择的晶体管布图不会适当地操作，但在指型布图中具有相对导电类型(P，N)的狭窄层交替地配置在芯片衬底中或配置在芯片衬底的表面上，从而防止任何严重的涡电流流动。
图2a中说明包含于图1的单片集成电路的晶体管11中的最小晶体管单元的高度放大示意布图图。所述单元包含中心漏极指状物14a和配置在所述中心漏极指状物14a的任一侧上的两个栅极指状物13a及b。在所述栅极指状物13a及13b中的每一者外部，形成个别离子注入源极区域21-b。
图2b中以沿着线A-A截取的横截面图来说明图2a的晶体管单元。芯片包含衬底22，在衬底22的上部中形成N+掺杂漏极区域23。源极区域21-b通过P+掺杂散热区域(P+doped sinker region)24而与N+掺杂漏极区域23分离。
形成于所述结构的顶上的介电钝化层25，和形成于其上且在电路的一些金属化层中的电感器26的一部分表示为阱。可通过以导电材料填充的通孔(via hole)以常规方式来制成从金属化层向下到漏极指状物14a和栅极指状物13a及13b的接触器。通常，源极区域21-b借助于衬底表面上的金属层接触器而电气连接到P+掺杂散热区域24。经由这些金属层接触器，源极区域21a及21b通常如上文所指示而接触到衬垫的后侧处。
所属领域的技术人员应了解，通常用于RF功率放大器的大晶体管器件包含图2a及图2b中所说明的大量的最小晶体管单元。
图3中说明本发明可适用的以等级A操作的单片集成标准功率放大器的电路图。即使大多数功率放大器不以等级A操作，但它们具有类似元件。功率放大器包含晶体管11、螺旋电感器12、DC阻塞电容器和谐振电路(tank circuit)32，所述谐振电路32包括电感器L、电容器C和电阻器R。
所述晶体管11为如上文所述的指型，且连接到所述电感器12和所述电容器13，以分别阻塞RF和DC电流。将谐振电路32调到共振频率，使得负载变成有电阻性的。电感器12以及电容器31必须较大以便令人满意地操作。根据此描述内容的任何其它优选实施例，电感器12配置在芯片上的晶体管11的顶上。
涡电流通常会出现在具有有效导电性的晶体管的任何一层中。这些以重要性的次序包括共用栅极和共漏连接，以及任选地(如果源极不连接在衬底的后侧处)，作为金属互连线的共用源极连接件、衬底、反型层、栅极、源极和漏极扩散区(即，掺杂的漏极和源极区域)。然而，对于指型功率放大器晶体管而言，栅极和反型层变得不重要，因为它们不允许有效半径的任何环电流。为了减少源极和漏极扩散区中与共用栅极和漏极以及可选地源极连接件中的涡电流，并使所述涡电流变得无效，如从上方所见，电感器仅覆盖晶体管的指状物。最终，衬底将总是对电感器的Q值作最终限制，但通过本发明避免或减少了其它影响。
图4中说明根据本发明进一步优选实施例的单片集成电路的高度放大示意布图图。晶体管11包含如上文所述的由共栅连接15互连的栅极指状物13a至13f和由共漏连接16互连的漏极指状物14a至14c。然而，此实施例包含略小的螺旋电感器41。所述螺旋电感器经配置，使得如从上方所见，其覆盖栅极指状物13a至13f中的复数个(即13b至13d)的至少一部分，且如从上方所见，使栅极和漏极连接件15、16保持未被覆盖。优选地，应将与晶体管指状物平行的最小数目的绕组直接放置于指状物的上面，因为与垂直于晶体管指状物流动的涡电流相比，沿着指状物的涡电流更难以解决。
图5中说明根据本发明又一进一步优选实施例的单片集成电路的高度放大示意布图图。所述集成电路包含配置在长且窄的晶体管51的顶上的多个螺旋电感器52、53，其中仍避免涡电流。所说明的晶体管51包含栅极指状物13a至13k和交错的漏极指状物14a至14f。栅极指状物13a至13k连接到共栅连接15，且漏极指状物14a至14f连接到共漏连接16。源极连接在芯片的后侧处。
应了解，虽然本发明主要希望供基于硅的RF功率集成电路使用，但其仍可在例如GaAs的其它材料系统中实现且/或为其它种类的应用而实现。
应进一步了解，在不脱离本发明的情况下，晶体管11完全可与具有指型布图的双极晶体管或MOS晶体管互换。如果所述双极晶体管为垂直晶体管，那么操作期间所使用的电流主要为垂直的，这使操作更不受横向环电流和涡电流的影响。指型布图在任何情况下均使这些横向电流最小化。

Claims (9)

1.一种单片集成电路，尤其一种用于射频应用的集成电路，其包含一晶体管和一螺旋电感器，所述单片集成电路的特征在于：
所述螺旋电感器(12；26；41；52，53)配置在所述晶体管(11；51)的顶上，藉此获得所述螺旋电感器与所述晶体管之间的一电磁耦合，且
所述晶体管具有一指型布图(13a至13k，14a至14f)以防止发生由所述电磁耦合导致的任何有效涡电流。
2.根据权利要求1所述的集成电路，其中所述螺旋电感器的一横向尺寸与所述晶体管的一横向尺寸具有相同的数量级。
3.根据权利要求1或2所述的集成电路，其中所述螺旋电感器与所述晶体管具有类似的横向延伸部分。
4.根据权利要求1至3中任一权利要求所述的集成电路，其中所述螺旋电感器(12)形成于所述集成电路的金属化层，优选地为上金属化层中，所述金属化层仅通过一钝化层(25)而与所述晶体管分离。
5.根据权利要求1至4中任一权利要求所述的集成电路，其中所述晶体管(11)与所述螺旋电感器(12)之间的一垂直距离小于25微米，优选地小于10微米，且最优选小于几微米。
6.根据权利要求1至5中任一权利要求所述的集成电路，其中所述晶体管为一RF功率放大器晶体管，且所述螺旋电感器为一RF阻塞电感器。
7.根据权利要求1至6中任一权利要求所述的集成电路，其中所述晶体管为一LDMOS晶体管。
8.根据权利要求1至7中任一权利要求所述的集成电路，其中
所述晶体管包含多个栅极指状物和多个漏极指状物；且
如从上方所见，所述螺旋电感器覆盖多个栅极指状物中的复数个的至少一部分，且如从上方所见，使得分别使所述多个栅极和漏极指状物互连的共栅极和漏极连接(15，16)保持未被覆盖。
9.根据权利要求1至8中任一权利要求所述的集成电路，其中所述集成电路包含配置在所述晶体管的顶上的多个螺旋电感器。
CNB2004800398992A 2004-01-09 2004-12-22 用于射频应用的单片集成电路 Expired - Fee Related CN100499109C (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102403316A (zh) * 2010-08-12 2012-04-04 飞思卡尔半导体公司 单片微波集成电路
CN103905012A (zh) * 2014-03-27 2014-07-02 北京工业大学 可小型化设计的电感

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5366932B2 (ja) * 2007-05-08 2013-12-11 スキャニメトリクス，インコーポレイテッド 超高速信号送受信
CN102624225A (zh) * 2011-01-28 2012-08-01 精材科技股份有限公司 电源模组及其封装方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2211987B (en) 1987-10-30 1992-01-02 Plessey Co Plc Circuit arrangement including an inductor and a mesfet
JP3036233B2 (ja) * 1992-06-22 2000-04-24 松下電器産業株式会社 半導体装置およびその製造方法
TW262595B (zh) * 1993-11-17 1995-11-11 Ikeda Takeshi
US5815014A (en) * 1996-06-28 1998-09-29 The Whitaker Corporation Transistor based frequency multiplier
US5789799A (en) * 1996-09-27 1998-08-04 Northern Telecom Limited High frequency noise and impedance matched integrated circuits
US6236101B1 (en) * 1997-11-05 2001-05-22 Texas Instruments Incorporated Metallization outside protective overcoat for improved capacitors and inductors
US6087723A (en) * 1998-03-30 2000-07-11 Micron Technology, Inc. Vertical surface mount assembly and methods
EP0966040A1 (en) * 1998-06-19 1999-12-22 International Business Machines Corporation Passive component above isolation trenches
JP3425573B2 (ja) * 1999-05-19 2003-07-14 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4005762B2 (ja) * 1999-06-30 2007-11-14 株式会社東芝 集積回路装置及びその製造方法
US6455915B1 (en) * 2000-05-30 2002-09-24 Programmable Silicon Solutions Integrated inductive circuits
JP2002164512A (ja) * 2000-11-28 2002-06-07 Fujitsu Ltd 半導体装置及びその製造方法
JPWO2002056381A1 (ja) * 2001-01-16 2004-05-20 ソニー株式会社 半導体装置及びその製造方法
US6342424B1 (en) * 2001-04-06 2002-01-29 National Semiconductor Corp. High-Q spiral inductor structure and methods of manufacturing the structure
JP3898024B2 (ja) * 2001-10-19 2007-03-28 Ｎｅｃエレクトロニクス株式会社 集積回路及びその製造方法
JP2003282582A (ja) * 2002-03-26 2003-10-03 Hitachi Ltd 半導体装置の製造方法
JP4355128B2 (ja) * 2002-07-04 2009-10-28 富士通マイクロエレクトロニクス株式会社 半導体装置およびその製造方法
KR100698617B1 (ko) * 2005-02-15 2007-03-21 삼성전자주식회사 집적 인덕터를 포함한 집적회로
US20080157222A1 (en) * 2006-12-27 2008-07-03 Mediatek Inc. Rf integrated circuit device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102403316A (zh) * 2010-08-12 2012-04-04 飞思卡尔半导体公司 单片微波集成电路
US9508599B2 (en) 2010-08-12 2016-11-29 Freescale Semiconductor, Inc. Methods of making a monolithic microwave integrated circuit
US9871008B2 (en) 2010-08-12 2018-01-16 Nxp Usa, Inc. Monolithic microwave integrated circuits
CN103905012A (zh) * 2014-03-27 2014-07-02 北京工业大学 可小型化设计的电感
CN103905012B (zh) * 2014-03-27 2017-06-06 北京工业大学 可小型化设计的电感

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CN100499109C (zh) 2009-06-10
SE526360C2 (sv) 2005-08-30
SE0400035L (sv) 2005-07-10
US8260245B2 (en) 2012-09-04
US20070176724A1 (en) 2007-08-02
US20120319200A1 (en) 2012-12-20
US20100109092A1 (en) 2010-05-06
SE0400035D0 (sv) 2004-01-09
US7536166B2 (en) 2009-05-19

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