CN1902743A - 集成电路技术中的低应力侧壁间隔件 - Google Patents
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Abstract
本发明提供一种形成具半导体衬底(102)之集成电路的方法(900)。栅极介电质(104)系形成于该半导体衬底(102)上，并且形成栅极(106)于该栅极介电质(104)上。形成数个源极/漏极接合面(304)(306)于该半导体衬底(102)内。使用低功率等离子增强化学汽相沉积过程形成一侧壁间隔件(402)于该栅极(106)周围。形成硅化物(604)(606)(608)于该等源极/漏极接合面(304)(306)与该栅极(106)上，并且沉积层间介电质(702)于该半导体衬底(102)上方。然后，形成数个通至该硅化物(604)(606)(608)的接触(802)(804)(806)于该层间介电质(702)内。
Description
技术领域
本发明大致上系关于半导体技术，且更特别的是关于半导体装置之硅化(siliciding)。
背景技术
现代生活的各方面几乎都用到电子产品，而电子产品的核心就是集成电路。从飞机、电视到腕表的每样东西都会用到不少集成电路。
集成电路制造于硅晶圆内及上，系藉由极其复杂的系统产生，该系统需要数百或甚至数千个精密控制的制程的协调。每一个制成的半导体晶圆具有数百至数万个集成电路，各值数百或数千美元。
集成电路系由数百至数百万个个别的组件组成。半导体晶体管为常见组件之一。目前最常见且重要的半导体技术系以硅为基底，而且以硅为基底的最佳半导体装置则为互补金属氧化物半导体(CMOS)晶体管。
CMOS晶体管的主要组件一般是由硅衬底组成，其系具有数个包围隔离数个晶体管区之浅沟氧化物隔离区。在该硅衬底的上方，该等晶体管区系包含在氧化硅栅极或门极氧化物上的多晶硅栅极。该多晶硅栅极两侧的硅衬底系经轻度掺杂以便具有导电性。硅衬底的轻度掺杂区系以“源极/漏极浅接合面(shallow source/drain junction)”称之，系以多晶硅栅极底下的信道区隔开。在多晶硅栅极侧面的弧状氧化硅或氮化硅间隔件(称作“侧壁间隔件(sidwall spacer)”)可沉积额外的掺杂以形成该等源极/漏极浅接合面之重度掺杂区，系以“源极/漏极深接合面”称之。该等源极/漏极浅接合面及深接合面一并以“源极/漏极接合面(S/D junction)”称之。
也可将该侧壁间隔件形成为两层式间隔件，其系包含第一绝缘层(例如氧化物层)，再以第二绝缘层(例如氮化物层)覆盖该氧化物层。然后，加工两绝缘层以形成两层式间隔件。
为制成该晶体管，沉积一层氧化硅介电层以便覆盖该多晶硅栅极、该弧状间隔件以及该硅衬底。为提供该晶体管用之电性连接，于该氧化硅介电层内蚀刻数个通至该多晶硅栅极与该等源极/漏极接合面之开孔。用金属填满该等开孔藉以形成电接触(electrical contact)。为完成该等集成电路，该等接触系连接至该介电材料外部之额外的介电材料层次中额外的配线层次。
操作时，输入连到多晶硅栅极之栅极接触的输入讯号系控制由一源极/漏极接触通过一源极/漏极接合面通过该信道至另一源极/漏极接合面以及至另一源极/漏极接触的电流流量。
晶体管系藉由热成长栅极氧化物层于半导体晶圆之硅衬底上并且形成一多晶硅层于该栅极氧化物层上方而制成。分别图样化(patterned)及蚀刻该氧化物层与多晶硅层藉以分别形成该等栅极氧化物与多晶硅栅极。该等栅极氧化物与多晶硅栅极依序作为屏蔽以便形成该等浅源极/漏极区，此系藉由离子布植硼或磷杂质原子于硅衬底表面内。离子布植后接着用700℃以上的温度进行高温退火以便活化已植入的杂质原子藉以形成该等源极/漏极浅接合面。
沉积并且蚀刻一层氮化硅层藉以形成数个侧壁间隔件于该等栅极氧化物与多晶硅栅极侧表面周围。该等侧壁间隔件、该等栅极氧化物以及该等多晶硅栅极均作为原有的源极/漏极区用之屏蔽，此系藉由离子布植硼或磷杂质原子于该硅衬底表面内且植入及通过该等源极/漏极浅接合面。离子布植后接着再次以700℃以上的温度高温退火藉以活化已植入的杂质原子以便形成该等源极/漏极接合面。
该等晶体管形成之后，沉积一层氧化硅介电层于该等晶体管上方并且向下蚀刻数个通至该等源极/漏极接合面以及至该等多晶硅栅极的接触开孔。然后，用导电金属填满该等接触开孔并且藉由形成导电配线于其它的层间介电(interlayer dielectric，ILD)层内而予以互连。
随着晶体管尺寸的减小，已发现金属接触与硅衬底或多晶硅之间的电阻已增加到对晶体管效能有不良影响的程度。为减少电阻，而于金属接触与硅衬底或多晶硅之间形成一过渡材料(transition material)。最佳的过渡材料为硅化钴(CoSi2)与硅化钛(TiSi2)，然而也可能使用其它的材料。
该硅化物系藉由先涂布一薄层之钴或钛于该硅衬底的源极/漏极接合面与多晶硅栅极上方而形成的。该半导体晶圆系以800℃以上的温度进行一个或更多退火步骤，使得钴或钛与硅及多晶硅之间有选择性反应以形成金属硅化物。该制程一般称作“硅化”。由于浅沟氧化物与侧壁间隔件不会反应形成硅化物，该硅化物系对准于源极/漏极接合面与多晶硅栅极上方，所以该制程也被称作“自对准硅化”(self-alignedsiliciding或saliciding)。
不过，现有之硅化与自对准硅化都未能成功地解决所有将金属接触连接到硅的相关问题。
长期以来一直在寻找此等问题之解决方案，但先前的发展未能传授或建议任何解决方案，从而熟谙此艺者长期以来仍未找出此等问题之解决方案。
发明内容
本发明系提供一种形成集成电路的方法。一栅极介电层形成于一半导体衬底上，且形成一栅极于该栅极介电层上。形成数个源极/漏极接合面于该半导体衬底内。使用低功率等离子增强化学汽相沉积(PECVD，low power plasma enhanced chemical vapor deposition)制程在该栅极的周围形成一侧壁间隔件。于该源极/漏极接合面与该栅极上形成一硅化物，并且沉积一层间介电层于该半导体衬底上方。然后，在该层间介电质内形成数个通至该硅化物的接触。本方法显著降低该等接触与硅或多晶硅之间的电阻，可大幅改善集成电路之效能。该PECVD制程在约100瓦特至约200瓦特的低偏压功率范围内进行较佳。
本发明某些具体实施例系具有其它额外优点或可取代上述优点的其它优点。参考附图及以下的实施方式之详细说明，熟谙此艺者应可更加明白本发明诸项优点。
附图说明
图1系根据本发明制造中间阶段中之晶体管的视图；
图2系带有衬底层沉积于其上之图1结构；
图3系形成源极/漏极浅接合面于离子布植期间之图2结构；
图4系形成侧壁间隔件后之图3结构；
图5系形成源极/漏极深接合面于离子布植期间之图4结构；
图6系硅化物形成期间之图5结构；
图7系介电层沉积于硅化物、侧壁间隔件、及浅沟绝缘层的上方后之图6结构；
图8系金属接触形成后之图7结构；以及
图9系根据本发明方法制造硅化物之简化流程图。
(主要组件符号说明)
100晶体管 102半导体衬底
104栅极介电层 106栅极
108浅沟绝缘层 202衬底层
302离子布植 304，306源极/漏极浅接合面
402侧壁间隔件 502离子布植
504，506源极/漏极深接合面
604，606，608硅化物层 702介电层
802，804，806金属接触
具体实施方式
以下之描述系提出很多供彻底了解本发明之特定细节。不过，显然熟谙此艺者可实施本发明而不需该等特定细节。为避免使本发明模糊，未揭示某些习知组态及制程步骤之细节。此外，图标装置具体实施例之附图只部份图标且非实际尺寸，特别是，为求清晰而放大某些尺度。各图相同的组件均以相同的组件符号表示。
“水平”一词在此系界定为与衬底或晶圆平行之面。“垂直”系指与刚界定的水平面垂直的方向。其它，例如，“在...上”、“上面”、“下面”、“底部”、“顶部”、“侧面”(如“侧壁”)、“高于”、“低于”、“上方”、以及“下方”均相较于水平面界定。
请参考图1，其系根据本发明图标制造中间阶段中之晶体管100。
为形成该中间阶段，已将一栅极介电层(例如，氧化硅)与一导电栅极层(例如，多晶硅)沉积于一材料(例如，硅)之半导体衬底102上。诸层系经摹制与蚀刻形成一栅极介电层104与一栅极106。再进一步摹制(pattern)、蚀刻并且用氧化硅材料填满于该半导体衬底102以形成一浅沟绝缘层(STI)108。
请参考图2，其图标系具有一衬底层(liner layer)202沉积于其上之图1结构。该衬底层202，通常为氧化硅，系覆盖该半导体衬底102、该栅极介电质104、该栅极106以及该浅沟绝缘层108。该衬底层202可为蚀刻中止(etch stop)材料或植入物保护(implant-protection)材料。
请参考图3，其系图标离子布植302期间之图2结构，以形成源极/漏极浅接合面304与306。
该栅极106与该栅极介电层104系作为形成源极/漏极浅接合面304与306用之屏蔽，此系藉由离子布植302硼(B)或磷(P)杂质原子至该半导体衬底102表面内。离子布植302后接着在700℃以上的温度进行高温退火以便活化已植入杂质原子藉以形成源极/漏极浅接合面304与306。
请参考图4，其系图标形成一弧状侧壁间隔件402后之图3结构。该侧壁间隔件可为一绝缘材料，其系由下列各物组成之群中选出：氧化物、氮化物以及其组合。
该衬底层202，系用以防止植入物损害，已被去除且沉积及蚀刻一绝缘材料(例如，氮化物或氧化物)之侧壁间隔件层以形成该侧壁间隔件402之圆弧形状。用来形成该侧壁间隔件402之侧壁间隔件层通常是用等离子增强化学汽相沉积(PECVD)制程沉积。
PECVD制程是使用一些射频功率以便导引材料之离子沉积于目标表面，例如，该半导体衬底102。已发现以低偏压功率进行PECVD制程可降低或排除用来形成该侧壁间隔件402与该半导体衬底102的材料之间的应力。根据本发明，该PECVD制程系以低偏压功率进行。已发现PECVD制程在约100瓦特至约200瓦特的低偏压功率范围内进行可降低侧壁间隔件402与半导体衬底102之间的应力。因而改善晶体管100之效能。
请参考图5，其系图标离子布植502期间之图4结构，以形成源极/漏极深接合面504与506。
该侧壁间隔件402、该栅极106以及该浅沟绝缘层(STI)108系分别作为形成源极/漏极深接合面504与506用之屏蔽，此系藉由离子布植502硼(B)或磷(P)杂质原子至该半导体衬底102表面内且分别植入及通过该等源极/漏极浅接合面304与306。离子布植502后接着再一次在700℃以上的温度进行高温退火以便活化已植入杂质原子藉以形成该等源极/漏极深接合面504与506。
请参考图6，系根据本发明图标用于形成硅化物层604、606以及608的沉积过程602。硅化物层604与608系分别形成于源极/漏极深接合面504与506上方的半导体衬底102表面上，并且在该栅极106上形成该硅化物层606。
一般而言，有3种形成硅化物的方法。于一技术中，该沉积过程602系沉积一种纯金属于数个暴露的硅区(单晶与多晶硅两种)。之后，该金属与硅反应形成一称为第一阶段富金属硅化物。然后，去除未反应的金属，并且使业已存在的第一阶段生成物再与底下的硅反应藉以形成第二阶段富硅的硅化物。于第二种技术中，该沉积过程602包含共蒸镀(co-evaporation)金属与硅两者至暴露的硅层上。用例如电子束汽化金属及硅。然后，将蒸气吸引至晶圆上且遍布该硅层。于第三技术中，该沉积过程602包含共溅镀(co-sputtering)金属与硅两者至硅层表面。共溅镀需要使金属及硅材料由合成目标或分离目标实际脱落随后导引该合成材料至晶圆上。
对于具有接合面深度达1000埃(Angstroms；)等级的源极/漏极浅接合面的新型半导体装置来说，习知自对准硅化制程产生许多问题。特别是，于此等自对准硅化制程期间，某些现有的源极/漏极区会被消耗掉。
在使用钴作为耐火金属(refractory metal)时，于转换为金属硅化物的过程中，会消耗约为其两倍厚度之硅，例如，100埃厚的钴层会消耗约103埃的硅。此等消耗会减少存在于源极/漏极接合面内的掺杂物且对源极/漏极接合面的电子效能特性有不良的影响，从而劣化集成电路之效能。
当耐火金属为钛时，硅化钛系形成于金属接触之间，因为侧壁间隔件会随着集成电路变小而变小，从而在多晶硅栅极与源极/漏极接合面之间可能出现电容性耦合(capacitive-coupled)或完全导通的路径，同样，也劣化集成电路之效能。
尽管本发明可用各种耐火金属硅化物，然已发现硅化镍具有许多令人满意的特性。不过，硅化镍时，已发现硅化镍难以形成耐用的硅化镍。本发明人认为约100埃厚且带有粗糙表面的厚硅化物最能保护硅衬底且提供良好的附着力。
不过，超均匀的镍(ultra-uniform nickel)可形成极耐用的硅化镍。根据定义，超均匀的硅化物系意指厚度变化不大于总厚度约百分之3的硅化物层。
形成超均匀硅化超均匀镍(ultra-uniform nickel ultra-uniformsilicide)604、606与608之一实施例系藉由用很低功率的汽相沉积过程于暴露的硅区上沉积镍，此处很低功率系意指在500瓦特直流电以下，且较佳者在约400与300瓦特直流电之间的功率位准。
此外，以极缓慢速率进行金属沉积较佳，此系定义为：每秒7.0埃以下，且在约每秒6.8与6.0埃之间较佳。
更进一步，较佳以此等功率位准及沉积速率将硅化物沈积成厚度不超过50埃的超薄厚度藉以提供超均匀、超薄的硅化物。然后，用退火制程，例如用700℃左右的高温退火，将已沉积的硅化物金属转换为硅化物。
该硅化物604、606与608较佳由下列各金属组成之群中选出：钴、钛、镍、掺杂砷的镍、其合金、其化合物以及其组合物。
请参考图7，其系图标在沉积一介电层702于硅化物层604、606、与608、侧壁间隔件402以及浅沟绝缘层108的上方之后的图6结构。
于各种具体实施例中，该介电层702为具有4.2至3.9的中等介电常数之介电材料例如，氧化硅(SiOx)、正硅酸乙酯(TEOS)、硼磷硅酸盐(borophosphosilicate，BPSG)玻璃等等，或具有3.9以下至2.5的介电常数之低介电常数介电材料，例如掺氟的正硅酸乙酯(FTEOS)、氢硅倍半氧烷(hydrogen silsesquioxane，HSQ)、双苯并环丁烯(bis-benzocyclobutene，BCB)、正硅酸甲酯(TMOS)、八甲基环四硅氧烷(octamethylcyclotetrasiloxane，OMCTS)、六甲基二硅氧烷(HMDS)、硼化三甲基硅基(trimethylsilyl boride，SOB)、二乙醯氧基-二-第三-丁氧基硅烷(diacetoxyditertiarybutoxysilane，DADBS)、磷酸三甲基硅烷基酯(trimethylsilyl phosphate，SOP)等等。超低介电常数的介电材料(介电常数在2.5以下且市上有售)系包含市售之Teflon-AF、铁弗龙微乳液(Teflon microemulsion)、聚亚醯胺奈米泡沫(polimide nanofoam)、二氧化硅气凝胶(silica aerogel)、二氧化硅干凝胶(silica xerogel)以及具有中孔洞的二氧化硅(mesoporous silica)。中止层与覆盖层(使用处)的材料为例如，氮化硅(SixNx)或氮氧化硅(SiON)。
请参考图8，其系图标在形成金属接触802、804与806后之图7结构。
该等金属接触802、804与806系各自电性连接于硅化物层604、606与608，且分别连接至该源极/漏极深接合面504、该栅极106以及该源极/漏极深接合面506。
于各种具体实施例中，该等金属接触802、804与806的金属系例如，钽(Ta)、钛(Ti)、钨(W)、其合金以及其化合物。于其它具体实施例中，该等金属接触802、804与806系例如，铜(Cu)、金(Au)、银(Ag)、其合金以及其化合物，其中一种或更多上述元素带有扩散阻障层于其周围。
请参考图9，其系图标本发明方法900之简化流程图。本方法900系包含：于步骤902，提供一半导体衬底；于步骤904，形成一栅极介电质于该半导体衬底上；于步骤906，形成一栅极于该栅极介电质上；于步骤908，形成数个源极/漏极接合面于该半导体衬底内；于步骤910，使用低功率等离子增强化学汽相沉积过程形成一侧壁间隔件于该栅极周围；于步骤912，形成硅化物于该等源极/漏极接合面与该栅极上；于步骤912，沉积层间介电质于该半导体衬底之上方；并且于步骤914，形成数个通至该硅化物的接触于该层间介电质内。
尽管已利用最佳的特定实施模式描述本发明，应了解熟谙此艺者根据前述说明显然可做出许多替代、修改、以及变化。因此，本发明意图涵盖所有落入申请专利范围的精神与范畴内的替代、修改、与变化。上述说明或图标于附图的所有内容只具图解说明性且不具限定性。
Claims (10)
1.一种形成集成电路的方法(900)，其包含：
提供半导体衬底(102)；
形成栅极介电质(104)于该半导体衬底(102)上；
形成栅极(106)于该栅极介电质(104)上；
形成数个源极/漏极接合面(304)(306)于该半导体衬底(102)内；
使用低功率等离子增强化学汽相沉积过程，形成侧壁间隔件(402)于该栅极(106)周围；
形成硅化物(604)(606)(608)于该源极/漏极接合面(304)(306)以及该栅极(106)上；
沉积层间介电质(702)于该半导体衬底(102)上方；以及
形成数个至该硅化物(604)(606)(608)的接触(802)(804)(806)于该层间介电质内。
2.如权利要求1所述的方法(900)，其中：
形成该侧壁间隔件(402)的步骤是使用在约100瓦特至约200瓦特的范围内的低偏压功率等离子增强化学汽相沉积过程。
3.如权利要求1所述的方法(900)，其中：
形成该硅化物(604)(606)(608)的步骤是以极缓慢的沉积速率沉积硅化物金属。
4.如权利要求1所述的方法(900)，其中：
形成该硅化物(604)(606)(608)的步骤是使用超薄厚度的硅化物金属。
5.如权利要求1所述的方法(900)，其中：
沉积该层间介电质(702)的步骤是沉积具有介电常数为中、低或超低介电常数中至少一种的介电材料。
6.如权利要求1所述的方法(900)，其中：
形成至该硅化物(604)(606)(608)的接触(802)(804)(806)的步骤是使用钽、钛、钨、铜、金、银、其合金、其化合物或其组合物中的至少一种。
7.如权利要求1所述的方法(900)，其中：
形成该硅化物(604)(606)(608)的步骤是形成硅化镍。
8.如权利要求1所述的方法(900)，其中：
形成该硅化物(604)(606)(608)的步骤是形成掺杂砷的硅化镍。
9.如权利要求1所述的方法(900)，其中：
形成该硅化物(604)(606)(608)的步骤是使用低偏压功率沉积技术。
10.如权利要求1所述的方法(900)，其中：
形成该硅化物(604)(606)(608)的步骤是形成钴、钛、镍、其合金、其化合物或其组合物中的至少一种的硅化物。
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| US7741181B2 (en) * | 2007-11-06 | 2010-06-22 | International Business Machines Corporation | Methods of forming mixed gate CMOS with single poly deposition |
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| JPH0766406A (ja) * | 1993-08-25 | 1995-03-10 | Oki Electric Ind Co Ltd | サリサイド型ｍｏｓｆｅｔ及びその製造方法 |
| JPH07254574A (ja) * | 1994-03-16 | 1995-10-03 | Sony Corp | 電極形成方法 |
| JP2809113B2 (ja) * | 1994-09-29 | 1998-10-08 | 日本電気株式会社 | 半導体装置の製造方法 |
| JPH08186085A (ja) * | 1994-12-28 | 1996-07-16 | Nec Corp | 半導体装置の製造方法 |
| US5814545A (en) * | 1995-10-02 | 1998-09-29 | Motorola, Inc. | Semiconductor device having a phosphorus doped PECVD film and a method of manufacture |
| JP3572561B2 (ja) * | 1996-10-11 | 2004-10-06 | 富士通株式会社 | 半導体装置の製造方法 |
| US5858846A (en) * | 1997-08-04 | 1999-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Salicide integration method |
| JP2000133802A (ja) * | 1998-10-28 | 2000-05-12 | Nec Corp | 半導体装置とその製造方法 |
| KR100313510B1 (ko) * | 1999-04-02 | 2001-11-07 | 김영환 | 반도체 소자의 제조방법 |
| US6368988B1 (en) * | 1999-07-16 | 2002-04-09 | Micron Technology, Inc. | Combined gate cap or digit line and spacer deposition using HDP |
| US6040223A (en) * | 1999-08-13 | 2000-03-21 | Taiwan Semiconductor Manufacturing Company | Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits |
| KR100407684B1 (ko) * | 2000-06-28 | 2003-12-01 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
| US6483154B1 (en) * | 2000-10-05 | 2002-11-19 | Advanced Micro Devices, Inc. | Nitrogen oxide plasma treatment for reduced nickel silicide bridging |
| US6495460B1 (en) * | 2001-07-11 | 2002-12-17 | Advanced Micro Devices, Inc. | Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface |
| US6664172B2 (en) * | 2002-01-22 | 2003-12-16 | United Microelectronics Corp. | Method of forming a MOS transistor with improved threshold voltage stability |
| US7005376B2 (en) * | 2003-07-07 | 2006-02-28 | Advanced Micro Devices, Inc. | Ultra-uniform silicides in integrated circuit technology |
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2004
- 2004-01-12 US US10/756,023 patent/US7005357B2/en not_active Expired - Lifetime
- 2004-12-21 DE DE112004002638T patent/DE112004002638B4/de active Active
- 2004-12-21 CN CNA200480040305XA patent/CN1902743A/zh active Pending
- 2004-12-21 GB GB0615073A patent/GB2425405B/en not_active Expired - Fee Related
- 2004-12-21 JP JP2006549314A patent/JP5265872B2/ja not_active Expired - Fee Related
- 2004-12-21 KR KR1020067013975A patent/KR20060123481A/ko not_active Application Discontinuation
- 2004-12-21 WO PCT/US2004/043109 patent/WO2005071729A1/en active Application Filing
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2005
- 2005-01-07 TW TW094100442A patent/TWI355733B/zh not_active IP Right Cessation
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|---|---|
| GB2425405A (en) | 2006-10-25 |
| JP5265872B2 (ja) | 2013-08-14 |
| US7005357B2 (en) | 2006-02-28 |
| DE112004002638B4 (de) | 2009-11-26 |
| JP2007518274A (ja) | 2007-07-05 |
| KR20060123481A (ko) | 2006-12-01 |
| DE112004002638T5 (de) | 2007-02-01 |
| WO2005071729A1 (en) | 2005-08-04 |
| US20050153496A1 (en) | 2005-07-14 |
| GB0615073D0 (en) | 2006-09-06 |
| TW200527649A (en) | 2005-08-16 |
| GB2425405B (en) | 2008-08-20 |
| TWI355733B (en) | 2012-01-01 |
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