TWI355733B - Low stress sidewall spacer in integrated circuit t - Google Patents
Low stress sidewall spacer in integrated circuit t Download PDFInfo
- Publication number
- TWI355733B TWI355733B TW094100442A TW94100442A TWI355733B TW I355733 B TWI355733 B TW I355733B TW 094100442 A TW094100442 A TW 094100442A TW 94100442 A TW94100442 A TW 94100442A TW I355733 B TWI355733 B TW I355733B
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- Prior art keywords
- forming
- gate
- dielectric
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- 125000006850 spacer group Chemical group 0.000 title claims description 24
- 239000000758 substrate Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 25
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 13
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000003989 dielectric material Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
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- 239000010949 copper Substances 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 61
- 229910052732 germanium Inorganic materials 0.000 description 14
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 6
- 229910052707 ruthenium Inorganic materials 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
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- 239000012535 impurity Substances 0.000 description 5
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
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- 229910052744 lithium Inorganic materials 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QIGBRXMKCJKVMJ-UHFFFAOYSA-N Hydroquinone Chemical compound OC1=CC=C(O)C=C1 QIGBRXMKCJKVMJ-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
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- 150000002500 ions Chemical group 0.000 description 2
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- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 1
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- 239000004965 Silica aerogel Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- OPARTXXEFXPWJL-UHFFFAOYSA-N [acetyloxy-bis[(2-methylpropan-2-yl)oxy]silyl] acetate Chemical compound CC(=O)O[Si](OC(C)=O)(OC(C)(C)C)OC(C)(C)C OPARTXXEFXPWJL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
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- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 150000001622 bismuth compounds Chemical class 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 150000001785 cerium compounds Chemical class 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- RGXWDWUGBIJHDO-UHFFFAOYSA-N ethyl decanoate Chemical compound CCCCCCCCCC(=O)OCC RGXWDWUGBIJHDO-UHFFFAOYSA-N 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000009830 intercalation Methods 0.000 description 1
- 230000002687 intercalation Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000004530 micro-emulsion Substances 0.000 description 1
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- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 239000008208 nanofoam Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- HMMGMWAXVFQUOA-UHFFFAOYSA-N octamethylcyclotetrasiloxane Chemical compound C[Si]1(C)O[Si](C)(C)O[Si](C)(C)O[Si](C)(C)O1 HMMGMWAXVFQUOA-UHFFFAOYSA-N 0.000 description 1
- 239000010450 olivine Substances 0.000 description 1
- 229910052609 olivine Inorganic materials 0.000 description 1
- GKEBANQXMVUDHF-UHFFFAOYSA-H oxalate;ruthenium(3+) Chemical compound [Ru+3].[Ru+3].[O-]C(=O)C([O-])=O.[O-]C(=O)C([O-])=O.[O-]C(=O)C([O-])=O GKEBANQXMVUDHF-UHFFFAOYSA-H 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- UZLYXNNZYFBAQO-UHFFFAOYSA-N oxygen(2-);ytterbium(3+) Chemical compound [O-2].[O-2].[O-2].[Yb+3].[Yb+3] UZLYXNNZYFBAQO-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910002028 silica xerogel Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- 210000003802 sputum Anatomy 0.000 description 1
- 208000024794 sputum Diseases 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 150000004772 tellurides Chemical class 0.000 description 1
- LFQCEHFDDXELDD-UHFFFAOYSA-N tetramethyl orthosilicate Chemical compound CO[Si](OC)(OC)OC LFQCEHFDDXELDD-UHFFFAOYSA-N 0.000 description 1
- FVCJARXRCUNQQS-UHFFFAOYSA-N trimethylsilyl dihydrogen phosphate Chemical compound C[Si](C)(C)OP(O)(O)=O FVCJARXRCUNQQS-UHFFFAOYSA-N 0.000 description 1
- 125000000026 trimethylsilyl group Chemical group [H]C([H])([H])[Si]([*])(C([H])([H])[H])C([H])([H])[H] 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- 229910003454 ytterbium oxide Inorganic materials 0.000 description 1
- 229940075624 ytterbium oxide Drugs 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
B55T5T 九、發明說明： [發明所屬之技術領域] 且更特別的是關於 本發明大致上係關於半導體技術 半導體裝置之矽化（siHciding)。 [先前技術] 到電子產品，而電子產品 電視到腕錶的每樣東西都
現代生活的各方面幾乎都用 的核心就是積體電路。從飛機、 會用到不少積體電路。 積體電路製造於矽晶圓内 統產生，該系統需要數百或甚 協調。每一個製成的半導體晶 路，各值數百或數千美元。 及上，係藉由極其複雜的系 至數千個精密控制的製程的 圓具有數百至數萬個積體電
積肢電路係由數百至數百萬個個別的元件址成 體電晶體為常見元件之—。目前最常見且重要的半導 術係以♦為基底’而且以⑪為基底的最佳半導 互補金屬氧化物半導體（CM〇s)電晶體。 、丨為 CMOS電晶體的主要元件一般是由矽基板組成，其係 具有數個包圍隔離數個電晶體區之淺溝氧化物隔離區。在 該石夕基板的上方，料電晶體區係包含在氧切閘極或間 極氧化物上的多晶残極。該多晶㈣極兩侧㈣基板係 經輕度摻雜錢具有導電性。⑪基板的輕度摻雜區係以 源極/汲極淺接面（shaII〇w s〇職心也juncti〇n)，，稱 之’係以多晶矽閘極底下的通道區隔開。在多晶矽閘極側 面的弧狀氧化矽或氮化矽間隔件（稱作“側壁間隔件 92753修正本 5 (s】dwa】】 spacer)”）可沈積額外的摻雜以形成該等源極/汲 極淺接面之重度摻雜區’係以“源極/沒極深接面，，稱之。 該等源極/沒極淺接面及深接面—併以“源極/㈣接面 (S/D junction)” 稱之。 也可將該側壁間隔件形成為兩層式間隔件，其係包含 第-絕緣層(例如氧化物層)’再以第二絕緣層(例如氮化物 層）覆蓋該氧化物層。铁後，& τ ^ μ & „ 一 …' 俊加工兩纟巴緣層以形成兩層式間 隔件。 為製成該電晶體，沈積一層氧化石夕介電層以便覆蓋該 少晶石夕閑極、該弧狀間隔件以及該％基板。為提供該電晶 體用之電J·生連接’於该氧化矽介電層内蝕刻數個通至該多 晶=閘極與該等源極/没極接面之開孔1金屬填滿該等開 孔藉以形成電接觸（electneal eGntaet)。為完成該等積體電 路’該等接觸係連接线介電材料敎額外的介電材料 層次中額外的配線層次。 么操作犄，輸入連到多晶矽閘極之閘極接觸的輸入訊號 知控制由一源極/汲極接觸通過一源極/汲極接面通過該通 道至另一源極/汲極接面以及至另一源極/汲極接觸的電流 流量。 電晶體係藉由熱成長閘極氧化物層於半導體晶圓之矽 基板上並且形成一多晶矽層於該閘極氧化物層上方而製 ，。分別圖樣化（patterned)及蝕刻該氡化物層與多晶矽層 藉以刀別形成該等閘極氧化物與多晶矽閘極。該等閘極氧 化物與多晶；^閘極依序作為遮罩以便形成該等淺源極/汲 6 92753修正本 1355733 極區’此係藉由離子佈植硼 内。離早佑始仫社从 貝项于於石夕基板表面 二植後接者用戰以上的溫度進行高溫退火以 '尤積雜：原子藉以形成該等源極/汲極淺接面。 於該；二二2:=形成數個側壁_ 源極/沒極區用之遮罩，此= :㈣極均作為原有的 ·'匕係精由離子佈植硼或磷雜質原子
於該石夕基板表面内且植入及通過該等源極/汲極淺接面。離 子佈植後接著再次α 7啊以上的溫度高溫退火藉以活化 已植入的雜質原子以便形成該等源極/汲極接面。 該等電晶體形成之後，沈積一層氧化石夕介電層於該等 電晶體上方並且向下姓刻數個通至該等源極/沒極接面以 及至該等多晶石夕閘極的接觸開孔。然後’用導電金屬填滿 該等接觸開孔並且藉由形成導電配線於其他的層間介電 (interlayer dielectric ’ ILD)層内而予以互連。 隨著電晶體尺寸的減小，已發現金屬接觸財基板或 多晶石夕之間的電阻已增加到對電晶體效能有不良影響的程 度。為減少電阻，而於金屬接觸與矽基板或多晶矽之間形 成一過渡材料（transition materia十最佳的過渡材料為矽化 鈷（CoSi2)與矽化鈦（TiSi2)，然而也可能使用其他的材料。 該等矽化物係藉由先塗佈一薄層之鈷或鈦於該矽基板 的源極/汲極接面與多晶矽閘極上方而形成的。該半導體晶 圓係以800°C以上的溫度進行一個或更多退火步驟，使得 钻或鈦與矽及多晶矽之間有選擇性反應以形成金屬矽化 92753修正本 7 物。該製裎一般稱作“矽化”。由於淺溝氧化物與側壁間 隔件不會反應形成矽化物，該等矽化物係對準於源極/汲極 接面與多晶矽閘極上方，所以該製程也被稱作“自對準矽 化（self-aligned siliciding 或 saliciding)。 不過，現有之矽化與自對準矽化都未能成功地解決所 有將金屬接觸連接到矽的相關問題。 ' 長期以來一直在尋找此等問題之解決方案，但先前的 _發展未能傳授或建議任何解決方案，從而熟諳此藝者長期 -以來仍未找出此等問題之解決方案。 [發明内容] 本發明係提供一種形成積體電路的方法。一閘極介電 層形成於一半導體基板上’且形成一間極於該間極介電層 上。形成數個源極/汲極接面於該半導體基板内。使用低功 率電漿輔助化學氣相沈積（PECVD，1〇w ρ_Γ Wa _anced chemical ν_ 製程在該問極的周圍 形成一側壁間隔件.。於該源極/汲極接面與該間極上形成一 :化物’並且沈積一層間介電層於該半導體基板上方。然 在該層間"電貝内形成數個通至該石夕化物的接觸。本 方法顯著降低該等接觸財或多晶♦之間的電阻，可大幅 改善積體電路之效能。肖PECVD製程在約⑽瓦特至約 200瓦特的低偏壓功率範圍内進行較佳。 本發明某些具體實施例係具有其他額外優點或可取代 上述優點的其他優點。夂去国n 慢點#考附圖及以下的實施方式之詳細 έ兄明’熟諳此藝者應可更加心本發明諸項優點。 92753修正本 8 1355733 [實施方式] 〜以下之描述係提出报多供徹底瞭解本發明之特定細 即。不過’顯㈣諸此藝者可實施本發明而不需該等特定 細節。為避免使本發明模糊，未揭示某些習知組態及製程 步驟之細節。此外’圖示裝置具體實施例之附圖只部份^ 示且非實際尺寸，特別是，為求清晰而放大某些尺度。各 圖相同的元件均以相同的元件符號表示。 “ 水平一 s司在此係界定為與基板或晶圓平行之面。 “垂直’’係指與剛界定的水平面垂直的方向。其他，例如， “在…上”、“上面”、“下面，，、“底部’，、“頂部”、 侧面（如“側壁”）、“高於，，、“低於”、“上方，、 以及“下方，’均相較於水平面界定。 請參考第1圖，其係根據本發明圖示製造中間階段中 之電晶體1〇〇。 為形成該中間階段，已將一閘極介電層（例如，氧化矽） 與:導電閘極層（例如，多晶矽）沈積於一材料（例如，矽） 之半導體基板102上。諸層係經摹製與蝕刻形成一閘極介 電層104與一閘極10“再進一步摹製（pattern)、蝕刻並且 用氧化矽材料填滿於該半導體基板102以形成一淺溝絕緣 層（STI)l〇8。 、 〇月參考弟2圖’其圖示係具有一概底層（Hner 沈積於其上之第1圖結構。該襯底層202，通常為氧化矽， 係覆蓋該半導體基板1〇2、該閘極介電質1〇4、該閘極1〇6 以及該淺溝絕緣層108。該襯底層202可為蝕刻中止（etch 9 92753修正本 1355733 stop)=料或植入物保護（impiam_pr〇tecti〇n)材料。 明參考第3圖，其係圖示離子佈植3〇2期間之第2圖 ，.’σ構以形成源極/沒極淺接面304與3 06。 該閘極1〇6與該閘極介電们〇4係作為形成源極/沒極 淺接面3〇4與3〇6用之遮罩，此係藉由離子佈植奶硼⑻ 或墙W雜Μ子至該半導體基板1Q2表面内。離子佈植 302後：著在700 C以上的溫度進行高溫退火以便活化已 丨植入雜質原子藉以形成源極/汲極淺接面304與306。 請參考第4圖，其係圖示形成一弧狀側壁間隔件4〇2 後之第3圖結構。該側壁間隔件可為一絕緣材料，其係由 下列各物組成之群中選出：氧化物、氮化物以及彼之組合。 該襯底層202，係用以防止植入物損害，已被去除且 沈積及㈣—絕緣材料（例如，氮化物或氧化物）之側壁間 隔件層以形成該側壁間隔件402之圓弧形狀。用來形成該 側壁間隔件402之側壁間隔件層通常是用電聚輔助化學氣 相沈積（PECVD)製程沉積。 PECVD製程係使用一些射頻功率以便導引材料之離 子沈積於目標表面，例如，該半導體基板1〇2。已發現以 低偏壓功率進行PECVD製程可降低或排除用來形成該側 壁間隔件4 0 2與該半導體基板】〇 2的材料之間的應力。根 據本發明，該PECVD製程係以低偏麗功率進行。已發現 D衣転在約1 〇〇瓦特至約2〇〇瓦特的低偏壓功率範圍 内進行可降低側壁間隔件4 〇 2與半導體基板】〇 2之間的應 力。因而改善電晶體！ 〇〇之效能。 92753修正本 丄乃5733 請參考第5圖，其係圖示離子佈植5〇2期間之4第圖 結構’以形成源極/汲極深接面504與506。 該側壁間隔件402、該閘極106以及該淺溝絕緣層 (ST1)108係分別作為形成源極/汲極深接面504與506用之 遮罩，此係藉由離子佈植5〇2硼或磷雜質原子至該 半導體基板102表面内且分別植入及通過該等源極/汲極 淺接面304與306。離子佈植502後接著再一次在7〇(Γ(：α 馨上=溫度進行高溫退火以便活化已植入雜質原子藉以形成 該等源極/汲極深接面504與506。 凊參考第6圖，係根據本發明圖示用於形成矽化物層 606以及608的沈積製程602。石夕化物層604與608 奋刀別形成於源極/沒極深接面5與506上方的半導體基 板102表面上，並且在該閘極1〇6上形成該矽化物層6〇6。 一般而言’有3種形成矽化物的方法。於一技術中， 該沈積製程602係沈積一種純金屬於數個暴露的矽區（單 曹晶與多晶石夕兩種）。之後，該金屬與石夕反應形成一稱為第一 階段富金屬矽化物。然後，去除未反應的金屬，並且使業 已存在的第一階段生成物再與底下的矽反應藉以形成第二 階段富矽的矽化物。於第二種技術中，該沈積製程6〇2包 含共洛It (co-evaporation)金屬與矽兩者至暴露的矽層上。 用例如電子束汽化金屬及矽。然後，將蒸氣吸引至晶圓上 且遍佈該矽層。於第三技術中，該沈積製程6〇2包含共濺 鍍（co-spmtering)金屬與矽兩者至矽層表面。共濺鍍需要使 金屬及矽材料由合成目標或分離目標實際脫落隨後導引該 92753修正本 合成材料至晶圓上。 對於具有接面深度達1〇〇〇埃 源極/汲極淺接面的新 ，）等級的 製程產生許多問題。特別t導Γ來說’習知自對準發化 待別疋，於此等自對準矽化* 某些現有的源極/汲極區會被消耗掉。彳化4期間’ 在使用料為耐火金屬（f_
金屬石夕化物的過程中，會消耗約為其 、^為 二埃厚的㈣會消 效能=極广面^咖物且對源極/沒極接面心 月匕：有不良的影響，從而劣化積體電路之效能。 、當耐火金屬為欽時，石夕化鈦係形成於金屬接觸， 因為側壁間P；%件會隨著積體電路變小而變小，從而在夕s
矽閘極與源極’汲極接面之間可能出ί見電容性耦I (capacitive-coupled)或完全導通的路徑同樣也劣化二 體電路之效能。 、
k g·本發明可用各種耐火金屬石夕化物，然已發現石夕化 鎳具有許多令人滿意的特性。不過，矽化鎳時，已發現矽 化鎳難以形成耐用的矽化鎳。本發明人認為約丨〇〇埃厚且 帶有粗糙表面的厚矽化物最能保護矽基板且提供良好的附 著力。 不過’超均勻的錄（ultra-uniform nickel)可形成極耐用 的石夕化錄。根據定義’超均勻的石夕化物係意指厚度變化不 大於總厚度約百分之3的石夕化物層。 形成起均勻石夕化超均勻鎳（ultra-uniform nickel 12 92753修正本 1355733
Ultra-Unif0rm silicide)604、606 與 608 之一實施例係藉由 用很低功率的氣相沈積製程於暴露的石夕區上沈積錄，此處 很低功率係意指在500瓦特直流電以下，且較佳者在約4⑼ 與300瓦特直流電之間的功率位準。 此外，以極緩慢速率進行金屬沈積較佳，此係定義為： 每秒7.0埃以下，且在約每秒68與6〇埃之間較佳。 更進一步，較佳以此等功率位準及沈積速率將矽化物 沈積成厚度不超過50埃的超薄厚度藉以提供超均勻、超薄 •的矽化物。然後，用退火製程，例如用7〇〇r左右的高溫 退火，將已沉積的矽化物金屬轉換為矽化物。 該等矽化物604、606與608較佳由下列各金屬組成之 群中選出.始、鈦、鎮、摻雜珅的錄、彼之合金、彼之化 合物以及彼之組合物。 請參考第7圖，其係圖示在沈積一介電層7〇2於矽化 物層604'606、與608、側壁間隔件402以及淺溝絕緣層108 的上方之後的第6圖結構。 φ 於各種具體實施例中，該介電層702為具有4.2至3.9 的中荨介電常數之介電材料例如’氧化石夕（Si〇χ)、正；5夕酸 乙酉旨（TEOS)、侧填石夕酸鹽（borophosphosilicate，BPSG)玻 璃等等’或具有3.9以下至2.5的介電常數之低介電常數 介電材料，例如摻氟的正矽酸乙酯（FTEOS)、氫矽倍半氧 烧（hydrogen silsesquioxane，HSQ)、雙苯并環丁稀 (bis-benzocyclobutene，BCB)、正石夕酸曱酯（TMOS)、八曱 基環四石夕氧烧（octamethylcyclotetrasiloxane，0MCTS)、六 甲基一碎乳烧（HMDS)、刪化三甲基碎基（trimethylsilyl boride，SOB)、二乙醯氧基-二-第三-丁氧基矽烷 13 92753修正本 1355733— (diacetoxyditertiarybutoxysilane，DADBS)、填酸三甲基石夕 烧基醋（trimethylsilyl phosphate，SOP)等等。超低介電常 數的介電材料（介電常數在2.5以下且市上有售）係包含市 售之 Teflon-AF ®、鐵弗龍微乳液（Teflon microemulsion)、 聚亞醯胺奈米泡沫（polimide nanofoam)、二氧化石夕氣凝勝 (silica aerogel)、二氧化石夕乾凝膠（silica xerogel)以及具有 中孔洞的二氧化矽（meS0p0r0US silica)。中止層與覆蓋層（使 用處）的材料為例如，氮化矽（SixNx)或氮氧化矽（Si〇N)。 請參考第8圖，其係圖示在形成金屬接觸8〇2、8〇4 與806後之第7圖結構。 該等金屬接觸802、804與806係各自電性連接於矽化 物層以)4、606與608，且分別連接至該源極/汲極深接面 504、該閘極1〇6以及該源極/汲極深接面。
於各種具體實施例中，該等金屬接觸8〇2、8〇4與8〇6 的金屬係例如，鈕(Ta)、鈦㈤、鎢(w)、彼之合金以及彼 ^化合物。於其他具體實施例中，該等金屬接觸観、謝 = 806係例如’銅（Cu)、金（Au)、銀（Ag)、彼之合金以及 合物’其中—種或更多上述元素帶有擴散阻障層於 月 > 考第9圖，其係圖示本發明方法_
圖。本方法900係包含：於步驟 "L 於步驟_ 驟9〇2’棱供-半導體基相 驟S’二，形成一間極介電f於該半導體基板上;於 數個細閘極於δ亥閘極介電質上；於步驟908,形 個源極/沒極接面於該半導體基板内；於步驟9ι〇，使 92753修正本 14 ^55733- - 門二ΐ =水輔助化學ι相沈積製程形成—側壁間隔件於該 ==·於步驟912，形成碎化物於該等源極/汲極接面 ^玄問極上：於㈣914’沈積層間介電質於該半導體基 觸：ϋ ’並且於步驟916，形成數個通至該矽化物的接 觸於δ玄層間介電質内。 ▲儘^已利用最佳的特定實施模式描述本發明，應瞭解 熟諳此*者根據前述說明顯然可做出許多替代、修改’、' 以 二:二―因此’本發明意圖涵蓋所有落入申請專利範圍的 精神與料内的替代、修改、與變化。上述說明或圖示於 附圖的所有内容只具圖解說明性且不具限定性。 、 [圖式簡單說明] 第1圖係根據本發明製造中間階段中之電晶 圖； 第2圖係帶有襯底層沈積於其上之第J圖結構； 冑3 ®㈣成祕/㈣淺接❹科佈植期間之第 着圖結構； 乐 第4圖係形成側壁間隔件後之第3圖結構； 第5圖係'形成源極/沒極深接面於離子佈植期 圖結構， 第6圖係矽化物形成期間之第5圖結構； 第7圖係介電層沈積於石夕化物、側壁間隔件、及淺 絕緣層的上方後之第6圖結構； / / 第8圖係金屬接觸形成後之第7圖結構；以及 第9圖係根據本發明方法製造石夕化物之簡化流程圖。 扣753修正本 TT55T33—~ 902, 904, 906, 908, 910, 912, 914, 916 [主要元件符號說明] 100 電晶體 104 閘極介電層 108 淺溝絕緣層 302 離子佈植 402 側壁間隔件 504, 506 源極/汲極深接面 604, 606, 608 矽化物層 802, 804, 806 金屬接觸 900 方法 102 半導體基板 106 閘極 202 襯底層 304, 306源極/汲極淺接面 502 離子佈植 702 介電層 步驟
16 92753修正本
Claims (1)
- 第94100442號專利申請案 100年7月28曰修正替換頁 1355733 _π • ' /c〇年7月4曰修正本j 十、申請專利範圍： 1. 一種形成積體電路之方法[900] ’其係包含： - 提供半導體基板[1〇2]; - 形成閘極介電質[104]於該半導體基板[1〇2]上； 形成閘極[106]於該閘極介電質[104]上； 形成數個源極/汲極接面[304] [306]於該半導體基 板[102]内；使用低功率電漿輔助化學氣相沈積製程，形成侧壁 間隔件[402]於該閘極[1〇6]周圍； 形成矽化物[604] [606] [608]於該等源極/汲極接面 [304] [306]與該閘極[1〇6]上； 沈積層間介電質[702]於該半導體基板[102]上方； 以及 形成數個通至該矽化物[604] [606] [608]的接觸 [802] [804] [806]於該層間介電質内， 其中，形成該矽化物[604] [606] [608]之步驟係使 用低偏壓功率沈積技術（low bias power deposition technique)，該低偏壓功率的功率位準介於大約300至 400瓦特直流電之間，而沉積速率介於每秒6.0至6.8 埃之間，以沉積具有超均勻並且超細厚度的金屬。 2.如申請專利範圍第1項之方法[900]，其中： 形成該側壁間隔件[402]之步驟係使用在約1〇〇瓦 特至約200瓦特的範圍内之低偏壓功率電漿輔助化學氣 相沈積製程。 17 92753(修正版) 1355733 - 第94100442號專利申請案 . 100年7月28日修正替換頁 I —— ’:3.如申請專利範圍第1項之方法[900]，其中： 沈積該層間介電質[702]之步驟係沈積具有介電常 數為中、低或超低介電常數中之至少一種之介電材料。 • 4.如申請專利範圍第1項之方法[900]，其中： 形成通至該矽化物[604] [606] [608]的該等接觸 [802] [804] [806]之步驟係使用組、欽、鎢、銅、金、 銀、彼之合金、彼之化合物或彼之組合物中之至少一種。 5.如申請專利範圍第1項之方法[900]，其中： Φ 形成該矽化物[604] [606] [608]之步驟係形成摻雜 珅之梦化鎳。18 92753(修正版)
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| US10/756,023 US7005357B2 (en) | 2004-01-12 | 2004-01-12 | Low stress sidewall spacer in integrated circuit technology |
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| US (1) | US7005357B2 (zh) |
| JP (1) | JP5265872B2 (zh) |
| KR (1) | KR20060123481A (zh) |
| CN (1) | CN1902743A (zh) |
| DE (1) | DE112004002638B4 (zh) |
| GB (1) | GB2425405B (zh) |
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| WO (1) | WO2005071729A1 (zh) |
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| US7132352B1 (en) * | 2004-08-06 | 2006-11-07 | Advanced Micro Devices, Inc. | Method of eliminating source/drain junction spiking, and device produced thereby |
| EP1949416A2 (en) * | 2005-09-23 | 2008-07-30 | Nxp B.V. | A method of fabricating a structure for a semiconductor device |
| US7465635B2 (en) * | 2006-09-21 | 2008-12-16 | Texas Instruments Incorporated | Method for manufacturing a gate sidewall spacer using an energy beam treatment |
| US7741181B2 (en) * | 2007-11-06 | 2010-06-22 | International Business Machines Corporation | Methods of forming mixed gate CMOS with single poly deposition |
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| JPH0766406A (ja) * | 1993-08-25 | 1995-03-10 | Oki Electric Ind Co Ltd | サリサイド型ｍｏｓｆｅｔ及びその製造方法 |
| JPH07254574A (ja) * | 1994-03-16 | 1995-10-03 | Sony Corp | 電極形成方法 |
| JP2809113B2 (ja) * | 1994-09-29 | 1998-10-08 | 日本電気株式会社 | 半導体装置の製造方法 |
| JPH08186085A (ja) * | 1994-12-28 | 1996-07-16 | Nec Corp | 半導体装置の製造方法 |
| US5814545A (en) | 1995-10-02 | 1998-09-29 | Motorola, Inc. | Semiconductor device having a phosphorus doped PECVD film and a method of manufacture |
| JP3572561B2 (ja) * | 1996-10-11 | 2004-10-06 | 富士通株式会社 | 半導体装置の製造方法 |
| US5858846A (en) | 1997-08-04 | 1999-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Salicide integration method |
| JP2000133802A (ja) * | 1998-10-28 | 2000-05-12 | Nec Corp | 半導体装置とその製造方法 |
| KR100313510B1 (ko) | 1999-04-02 | 2001-11-07 | 김영환 | 반도체 소자의 제조방법 |
| US6368988B1 (en) * | 1999-07-16 | 2002-04-09 | Micron Technology, Inc. | Combined gate cap or digit line and spacer deposition using HDP |
| US6040223A (en) * | 1999-08-13 | 2000-03-21 | Taiwan Semiconductor Manufacturing Company | Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits |
| KR100407684B1 (ko) * | 2000-06-28 | 2003-12-01 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
| US6483154B1 (en) * | 2000-10-05 | 2002-11-19 | Advanced Micro Devices, Inc. | Nitrogen oxide plasma treatment for reduced nickel silicide bridging |
| US6495460B1 (en) | 2001-07-11 | 2002-12-17 | Advanced Micro Devices, Inc. | Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface |
| US6664172B2 (en) | 2002-01-22 | 2003-12-16 | United Microelectronics Corp. | Method of forming a MOS transistor with improved threshold voltage stability |
| US7005376B2 (en) * | 2003-07-07 | 2006-02-28 | Advanced Micro Devices, Inc. | Ultra-uniform silicides in integrated circuit technology |
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| CN1902743A (zh) | 2007-01-24 |
| DE112004002638B4 (de) | 2009-11-26 |
| DE112004002638T5 (de) | 2007-02-01 |
| TW200527649A (en) | 2005-08-16 |
| JP2007518274A (ja) | 2007-07-05 |
| GB2425405A (en) | 2006-10-25 |
| KR20060123481A (ko) | 2006-12-01 |
| GB0615073D0 (en) | 2006-09-06 |
| US7005357B2 (en) | 2006-02-28 |
| JP5265872B2 (ja) | 2013-08-14 |
| GB2425405B (en) | 2008-08-20 |
| WO2005071729A1 (en) | 2005-08-04 |
| US20050153496A1 (en) | 2005-07-14 |
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