CN1846305A - 整合具有不同功函数的金属以形成具有高k栅极电介质及相关结构的互补金属氧化物半导体栅极的方法 - Google Patents

整合具有不同功函数的金属以形成具有高k栅极电介质及相关结构的互补金属氧化物半导体栅极的方法 Download PDF

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CN1846305A
CN1846305A CNA2004800255359A CN200480025535A CN1846305A CN 1846305 A CN1846305 A CN 1846305A CN A2004800255359 A CNA2004800255359 A CN A2004800255359A CN 200480025535 A CN200480025535 A CN 200480025535A CN 1846305 A CN1846305 A CN 1846305A
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metal oxide
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相奇
H·钟
J-S·古
A·K·霍尔布鲁克
J·S·千
G·J·克拉思
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Advanced Micro Devices Inc
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Abstract

依据一个示意性的实施例，提供一种在衬底(202)上整合第一(206)与第二金属层(208)以形成双金属NMOS栅极(226)及PMOS栅极(228)的方法，该方法包括在衬底(202)的NMOS区域(210)与PMOS区域(212)上沉积(150)介电层(204)。此方法还包括在介电层(204)上沉积(150)第一金属层(206)。此方法还包括在第一金属层(206)上沉积(150)第二金属层(208)。此方法还包括在衬底(202)的NMOS区域(210)中注入(152)氮，再将第一金属层(206)的第一部分转化(154)成金属氧化物层(220)以及将第一金属层(206)的第二部分转化成金属氮化物层(218)。此方法还包括形成(156)NMOS栅极(226)及PMOS栅极(228)，其中NMOS栅极(226)包括金属氮化物层(218)的区段(234)，且PMOS栅极(228)包括金属氧化物层(220)的区段(242)。

Description

整合具有不同功函数的金属以形成具有高K栅极电介质及相关结 构的互补金属氧化物半导体栅极的方法
技术领域
一般而言，本发明涉及半导体器件的领域。更具体地，本发明涉及互补金属氧化物半导体(“CMOS”)晶体管的领域。
背景技术
半导体业者可利用具有高介电常数(“高k”)的栅极电介质与金属栅极电极改良互补金属氧化物半导体(“CMOS”)晶体管的性能。在小特征尺寸技术上希望高k栅极电介质，这是由于传统的诸如二氧化硅的栅极电介质太薄以至于导致高的隧穿电流以及其它问题。此外，金属栅极电极可取代多晶硅栅极电极，这是因为多晶硅栅极电极例如具有高电阻且在栅极电介质与沟道间的界面造成非所希望的载流子损耗，以至于缩减NFET与PFET晶体管性能。然而，N型金属氧化物半导体(NMOS)晶体管需要具有，例如大约4.1eV的功函数的金属栅极，而P型金属氧化物半导体(PMOS)晶体管需要具有，例如大约5.1eV的更高功函数的金属栅极电极。因此，半导体业者需要在制造工艺中整合具有不同功函数的金属与高k电介质，以有效率地获得双金属NMOS与PMOS栅极。
在利用金属栅极电极与高k栅极电介质的CMOS晶体管的传统制造工艺中，通常在半导体芯片衬底的NMOS与PMOS区域上沉积具有适合于NMOS栅极的功函数的第一金属层与包括高k电介质的栅极介电层。由于NMOS与PMOS栅极的栅极电极需要不同的功函数，所以第一金属层可能不适合于形成PMOS栅极电极。此外，目前的高k电介质沉积工艺通常会产生高浓度的负电荷以在PMOS区域中形成高k介电层，其造成了栅极阈值电压的非所希望的移位以及载流子迁移率的降低。因此，在传统的工艺中，必须在NMOS与PMOS区域中提供不同的金属层以形成个别的NMOS与PMOS栅极电极。
因此，在传统的制造工艺中，移除位于衬底的PMOS区域中的第一金属层的部分并且在PMOS区域中的栅极介电层上沉积具有用于PMOS栅极的功函数的第二金属层。因此，上述讨论的制造双金属CMOS栅极的传统工艺是一种困难的工艺，其需要在衬底的NMOS与PMOS区域上沉积第一金属层、移除PMOS区域中的第一金属层的部分、并在PMOS区域中沉积第二金属层。
因此，本领域需要一种整合具有不同功函数的两种金属以形成具有高k栅极电介质的双金属CMOS栅极的有效方法。
发明内容
本发明涉及整合具有不同功函数的金属以形成具有高k栅极电介质及相关结构的CMOS栅极的方法。本发明提出并解决本领域中所需要的整合具有不同功函数的两种金属以形成具有高k栅极电介质的双金属CMOS栅极的有效方法。
依据一个示意性的实施例，一种在衬底上整合第一金属层与第二金属层以形成双金属NMOS及PMOS栅极的方法，包括在衬底的NMOS及PMOS区域上沉积介电层的步骤。介电层可以是，例如，氧化铪，氧化锆，硅酸锆，或氧化铪。此方法还包括在介电层上沉积第一金属层。第一金属层可以是，例如，铪，锆，或钽。此方法还包括在第一金属层上沉积第二金属层。第二金属层可以是，例如，铂，钨，镍，或钌。此方法还包括将氮注入衬底的NMOS区域中。
依据此示意性的实施例，此方法还包括将第一金属层的第一部分转化成金属氧化物层以及将第一金属层的第二部分转化成金属氮化物层。利用高温退火将第一金属层的第一部分转化成金属氧化物层，再完成将第一金属层的第二部分转化成金属氮化物层。此方法还可包括将P型掺杂物注入衬底的PMOS区域中。此方法还包括形成NMOS及PMOS栅极，其中NMOS栅极包括金属氮化物层的区段且PMOS栅极包括金属氧化物层的区段。PMOS栅极的栅极电极可以是第二金属层的区段且NMOS栅极的栅极电极可以是金属氮化物层的区段。在一个实施例中，本发明是利用上述讨论的方法所制造的CMOS器件。在阅读下列详细说明及附图后，本领域普通技术人员将可更轻易地了解本发明的其它特点与优点。
附图说明
图1是对应于依据本发明的一个实施例的示意性方法步骤的流程图；
图2A是说明对应于图1的流程图的某些步骤的依据本发明的实施例予以加工的晶片的部分的横截面图；
图2B是说明对应于图1的流程图的某些步骤的依据本发明的实施例予以加工的晶片的部分的横截面图；
图2C是说明对应于图1的流程图的某些步骤的依据本发明的实施例予以加工的晶片的部分的横截面图；
图2D是说明对应于图1的流程图的某些步骤的依据本发明的实施例予以加工的晶片的部分的横截面图；
图2E是说明对应于图1的流程图的某些步骤的依据本发明的实施例予以加工的晶片的部分的横截面图。
具体实施方式
本发明涉及整合具有不同功函数的金属以形成具有高k栅极电介质及相关结构的互补金属氧化物半导体(CMOS)栅极的方法。下述说明包含关于实施本发明的某些特定信息。本领域普通技术人员将会认可本发明可以不同于本申请案中所特定探讨的方式予以实施。此外，不讨论本发明的某些特定细节以避免模糊本发明。
本申请案中的附图及其随附的详细说明仅针对本发明示意性的实施例。为了保持简洁，本申请案中不特别说明本发明的其它实施例且不通过本案附图予以特别说明。
本发明涉及在半导体芯片的衬底上有效地整合不同金属层以形成具有高k栅极电介质的双金属NMOS及PMOS栅极的工艺。如以下将要详细讨论的，本发明实现了创新的工艺，通过利用第一选择性氮注入及高温退火以改变金属层的个别部分的组成与性质，获得双金属NMOS及PMOS栅极，并且利用第二选择性电荷平衡注入以平衡PMOS栅极电介质堆叠(stack)中的电荷。
图1显示了说明依据本发明实施例的示意性方法的流程图。对本领域普通技术人员显而易知的某些细节及特点已从流程图100中略去。例如，一个步骤可由一个或多个子步骤所组成或者可涵盖特定的设备或材料，如本领域中已知的。流程图100中所示的步骤150至158足以说明本发明的一个实施例，本发明的其它实施例可利用不同于那些流程图100中所示的步骤。注意流程图100中所示的加工步骤在步骤150之前于晶片(包含具有NMOS区域及PMOS区域的衬底)上执行。
此外，图2A、2B、2C、2D、及2E中的结构250、252、254、256、及258说明了在结构，如半导体芯片(包含上述讨论的衬底)上分别执行流程图100的步骤150、152、154、156、及158的结果。例如，结构250显示了执行加工步骤150后的上述讨论的结构，结构252显示了对结构250执行步骤152加工后的结构，结构254显示了对结构252执行步骤154加工后的结构，等等。
现在参照图1的步骤150及图2A的结构250，在流程图100的步骤150，在衬底202的NMOS区域210与PMOS区域212上依序地沉积介电层204、金属层206、及金属层208。衬底202可包括在PMOS区域212中的N型掺杂的硅且可包括在NMOS区域210中的P型掺杂的硅。介电层204可包括具有高介电常数的电介质(“高k电介质”)，如氧化铪、氧化锆、硅酸锆、或氧化铪，且可利用化学气相沉积(“CVD”)法或其它适当的方法沉积在衬底202上。举例而言，介电层204可具有小于30.0埃的厚度。
金属层206可包括铪、锆、或钽且可通过CVD法或物理气相沉积(“PVD”)法或其它适当的方法沉积在介电层204上。金属层206具有大约4.1eV的功函数，而4.1eV的功函数正是NMOS晶体管栅极所希望的功函数。举例而言，金属层206可具有大约30.0埃与大约100.0埃之间的厚度。金属层208可包括铂、钨、钴、镍、或钌，且可通过CVD工艺或PVD工艺或其它适当的工艺沉积在金属层206上。金属层208具有大约5.1eV的功函数，而5.1eV的功函数正是PMOS晶体管栅极所希望的功函数。举例而言，金属层208可具有大于100.0埃的厚度。在一个实施例中，可在金属层208上沉积多晶硅(polycrystalline silicon，“poly”)层(未示于任何附图中)。在该实施例中，多晶硅层在NMOS区域210中是N型掺杂且在PMOS区域212中是P型掺杂。在一个实施例中，可在金属层208上形成硅化物层(未示于任何附图中)。参照图2A，通过结构250说明流程图100的步骤150的结果。
继续图1的步骤152及图2B的结构252，在流程图100的步骤152，在衬底202的PMOS区域212上形成掩膜214。掩膜214可包括光刻胶或本领域中已知的其它适当的材料。掩膜214仅形成在PMOS区域212上，而NMOS区域210则未形成掩膜。接下来，在NMOS区域210上执行选择性氮注入216。在本实施例中，调整氮注入216使得氮在通过金属层208之际同时选择性地注入金属层206中。作为氮注入216的结果，注入金属层206中的氮的浓度高于注入金属层208中的氮的浓度。参照图2B，以结构252说明流程图100的步骤152的结果。
继续图1的步骤154及图2C的结构254，在流程图100的步骤154，从PMOS区域212移除掩膜214再执行高温退火，以在NMOS区域210中形成金属氮化物层218以及在PMOS区域212中形成金属氧化物层220。例如，掩膜214可利用等离子蚀刻或本领域中已知的其它适当的蚀刻予以移除。作为执行高温退火的结果，金属层206位于NMOS区域210中的部分转化成金属氮化物以形成金属氮化物层218(本申请案中也称为“氮化物转化”部分)，且金属层206位于PMOS区域212中的部分转化成金属氧化物以形成金属氧化物层220(本申请案中也称为“氧化物转化部分”)。金属氮化物层218提供NMOS晶体管栅极的适当的功函数。在后续工艺步骤中将利用金属氧化物层220的区段形成PMOS栅极电介质堆叠。
当金属层206在PMOS区域212中的部分在高温退火期间转化成金属氧化物时，金属层206的部分有效地转化成电介质。因此，高温退火通过将金属层206位于PMOS区域212中的部分转化成金属氧化物，改变金属层206位于PMOS区域212中作为电介质的部分的组成与性质。结果，当在后续工艺步骤中在PMOS区域212中形成PMOS栅极时，金属层208变成PMOS栅极中的PMOS栅极电极。参照图2C，通过结构254说明流程图100的步骤154的结果。
继续图1的步骤156及图2D的结构256，在流程图100的步骤156，在衬底202的NMOS区域210上形成掩膜222。类似于掩膜214，掩膜222可包括光刻胶或本领域中已知的其它适当的材料。掩膜222仅形成在NMOS区域210上，而PMOS区域212则未形成掩膜。接着，在PMOS区域212中执行选择性电荷平衡注入224。在选择性电荷平衡注入224中，将P型掺杂物如氩或其它适当的掺杂物注入PMOS区域212中的金属氧化物层220中。在本发明中，利用选择性电荷平衡注入224获得平衡的电荷，将适当的正电荷引入金属氧化物层220中，以中和金属氧化物层220及介电层204位于PMOS区域212中的部分中的负电荷。结果，本发明有利地防止由包括金属氧化物层220及介电层204的PMOS栅极电介质堆叠中的负电荷造成的在后续形成的PMOS栅极中的非所希望的阈值电压偏移及非所希望的载流子迁移率下降。参照图2D，通过结构256说明流程图100的步骤156的结果。
继续图1的步骤158及图2E的结构258，在流程图100的步骤158，从衬底202的NMOS区域210移除掩膜222。注意本申请案中结构258也称为“CMOS结构”。掩膜222可以类似于上述讨论的掩膜214的方式予以移除。接着，分别在NMOS区域210及PMOS区域212中形成NMOS栅极226及PMOS栅极228。可通过本领域中已知的方式将位于NMOS区域210中的金属层208、金属氮化物层218、以及介电层204予以图形化并蚀刻而形成NMOS栅极226。同样地，可通过将位于PMOS区域212中的金属层208、金属氧化物层220、及介电层204予以图形化并蚀刻而形成PMOS栅极228。
NMOS栅极226包括栅极电极堆叠230(包括金属层208的区段232及金属氮化物层218的区段234)、以及栅极电介质(包括介电层204的区段236)。NMOS栅极226的栅极电极堆叠230的功函数由金属氮化物层218的部分234予以决定。在其它实施例中，栅极电极堆叠230可包括位于金属层208的区段232上的多晶硅层或硅化物层。PMOS栅极228包括栅极电极238(包括金属层208的区段238)、以及栅极电介质堆叠240(包括金属氧化物层220的区段242及介电层204的区段244)。PMOS栅极228的栅极电极238的功函数由金属层208予以决定。在其它实施例中，PMOS栅极228可包含包括多晶硅层或位于金属层208的区段238上的硅化物层的栅极电极堆叠。注意虽然为了保持简洁而在图2E中仅显示NMOS栅极226及PMOS栅极228，但NMOS区域210及PMOS区域212可分别包括多数的NMOS栅极及PMOS栅极。参照图2E，通过结构258说明流程图100的步骤158的结果。
如上所讨论，通过利用选择性氮注入与电荷平衡注入，本发明有利地获得了具有适当功函数及高k栅极电介质的双金属NMOS及PMOS栅极。如上所讨论，在衬底的NMOS区域中执行选择性氮注入之后，利用高温退火将金属层206的部分有利地转化成金属氮化物层，结合该金属氮化物层与金属层208的区段以形成NMOS栅极电极堆叠。如上所讨论，还利用高温退火将金属层206的部分转化成金属氧化物层，利用结合该金属氧化物层与介电层204的区段以形成PMOS栅极电介质堆叠。本发明还利用选择性电荷平衡注入以中和PMOS栅极电介质堆叠(即栅极电介质堆叠240)中的过多的负电荷，可有利地防止PMOS栅极堆叠中的非所希望的栅极阈值电压偏移及载流子迁移率下降。
此外，通过利用衬底的NMOS区域及PMOS区域中的相同金属层，即金属层206及208，本发明有利地实现不同金属层(即金属层206及208)的有效整合，以获得双金属CMOS栅极，即NMOS及PMOS栅极。相反地，在传统的双金属CMOS栅极制造工艺中，以需要在NMOS及PMOS区域中分别沉积栅极金属的工艺来制造双金属CMOS栅极，其难以有效地实施。
由本发明的示意性实施例的上述说明，可明了可使用各种技术实施本发明的概念而不偏离其范围。此外，虽然本发明已由特定参考某些实施例而予以说明，但本领域普通技术人员将意识到在不偏离本发明的精神与范围下可改变形式及细节。所说明的例示实施例在各方面皆视为是说明而非限制。还应了解本发明并不局限于本文所述的特定例示实施例，而能够有许多重新配置、变化、及取代而不偏离本发明的范围。
因此，已说明整合具有不同功函数的金属以形成具有高k栅极电介质及相关结构的CMOS栅极的方法。

Claims (10)

1.一种方法，包括下述步骤：
在衬底(202)的N型金属氧化物半导体区域(210)与P型金属氧化物半导体区域(212)上沉积(150)介电层(204)；
在该介电层(204)上沉积(150)第一金属层(206)；
在该衬底(202)的该N型金属氧化物半导体区域(210)中注入(152)氮；
将该第一金属层(206)的第一部分转化(154)成金属氧化物层(220)以及将该第一金属层(206)的第二部分转化成金属氮化物层(218)；
形成(156)N型金属氧化物半导体栅极(226)与P型金属氧化物半导体栅极(228)，该N型金属氧化物半导体栅极(226)包括该金属氮化物层(218)的区段(234)且该P型金属氧化物半导体栅极(228)包括该金属氧化物层(220)的区段(242)。
2.如权利要求1所述的方法，其中将该第一金属层(206)的该第一部分转化(154)成该金属氧化物层(220)的步骤包括利用高温退火。
3.一种方法，包括在衬底(202)的N型金属氧化物半导体区域(210)与P型金属氧化物半导体区域(212)上沉积(150)介电层(204)、在该介电层(204)上沉积(150)第一金属层(206)的步骤，该方法的特征在于：
在该衬底(202)的该N型金属氧化物半导体区域(210)中注入(152)氮，将该第一金属层(206)的第一部分转化(154)成金属氧化物层(220)以及将该第一金属层(206)的第二部分转化成金属氮化物层(218)、形成N型金属氧化物半导体栅极(226)与P型金属氧化物半导体栅极(228)，该N型金属氧化物半导体栅极(226)包括该金属氮化物层(218)的区段(234)且该P型金属氧化物半导体栅极(228)包括该金属氧化物层(220)的区段(242)。
4.如权利要求3所述的方法，其中将该第一金属层的该第一部分该转化(154)成该金属氧化物层(220)的步骤包括利用高温退火。
5.如权利要求3所述的方法，在转化(154)该第一金属层(206)的该第一部分的步骤之后并且在形成(156)该N型金属氧化物半导体栅极(226)及该P型金属氧化物半导体栅极(228)的步骤之前，还包括将P型掺杂物注入(156)该衬底(202)的该P型金属氧化物半导体区域(212)中的步骤。
6.如权利要求3所述的方法，在沉积(150)该第一金属层(206)的步骤之后并且在该N型金属氧化物半导体区域(210)中注入(152)氮的步骤之前，还包括在该第一金属层(206)上沉积(150)第二金属层(208)的步骤。
7.如权利要求3所述的方法，其中在该N型金属氧化物半导体区域(210)中注入(152)氮的步骤包括在该第一金属层(206)的该第二部分中注入该氮而没有将该氮注入到该第一金属层(206)的该第一部分中。
8.如权利要求6所述的方法，其中该P型金属氧化物半导体栅极(228)的栅极电极包括该第二金属层(208)的区段(238)且该N型金属氧化物半导体栅极(226)的栅极电极包括该金属氮化物层(218)的区段(234)。
9.如权利要求3所述的方法，其中该第一金属层(206)是选自于由铪、锆、及钽所组成的组。
10.一种互补金属氧化物半导体(CMOS)器件，包括：
衬底(202)，该衬底(202)包括N型金属氧化物半导体区域(210)与P型金属氧化物半导体区域(212)；
N型金属氧化物半导体栅极电极堆叠(230)，其位于该N型金属氧化物半导体区域(210)中的该衬底(202)上，该N型金属氧化物半导体栅极电极堆叠(230)包括金属氮化物层(218)的区段(234)；
P型金属氧化物半导体栅极电介质堆叠(240)，其位于该P型金属氧化物半导体区域(212)中的该衬底(202)上，该P型金属氧化物半导体栅极电介质堆叠(240)包括金属氧化物层(220)的区段(242)；
其中该金属氮化物层(218)的该区段(234)由第一金属层(206)的第一部分所形成，且该金属氧化物层(220)的该区段(242)由该第一金属层(206)的第二部分所形成。
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