CN1828945A - 具有富硅氧化硅层的存储器件及其制造方法 - Google Patents
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Abstract
本发明公开了一种具有富硅氧化物层的存储器件及其制造方法。所述具有富硅氧化物层的存储器件包括半导体结构、形成在所述半导体衬底上的源极/漏极区、和形成在所述半导体衬底上的栅结构。所述栅结构与所述源极/漏极区接触并包括具有比二氧化硅层(SiO2)大的硅组分的氧化物层。
Description
技术领域
本发明涉及一种具有富硅氧化硅层的存储器件及其制造方法，且更具体而言，涉及一种包括由具有不同能带隙的介电层的多层结构形成的隧穿氧化物层的非易失存储器件及其制造方法。
背景技术
存储器件分类为易失存储器和非易失存储器。易失存储器的实例是动态随机存取存储器(DRAM)和静态随机存取存储器(SRAM)。易失存储器能在电源极保持施加时存取数据，但当移除电源极时数据消失。另一方面，即使移除电源极非易失存储器也能保持数据。典型的非易失存储器是闪存。
图1是常规非易失存储器、具体地是浮置栅极型闪存的截面图。
参照图1，掺杂有掺杂剂的第一掺杂区11a和第二掺杂区11b形成在半导体衬底10上。沟道区形成在所述第一掺杂区11a与第二掺杂区11b之间的半导体衬底10内。栅结构形成在与所述第一掺杂区11a和第二掺杂区11b接触的沟道区上。所述栅结构包括依次形成在所述沟道区上的隧穿氧化物层12、浮置栅极13、阻挡氧化物层14、和由导电材料形成的栅电极层15。隧穿氧化物层12可以由介电材料(例如氧化硅层)形成，且浮置栅极12可以由多晶硅形成。
在图1所示的常规非易失存储器中，浮置栅极13可以由多晶硅或氮化硅(Si3N4)形成，以保持用作存储电荷的电荷俘获区的俘获位置，或者必须形成硅纳米点。然而，具有上述结构的存储器件的制造方法的工艺要求高温热退火。在SONOS存储器的情况中，很难减小隧穿氧化物层12的厚度在3nm以下，因为俘获位置的带隙分布是不均匀的。虽然由于隧穿氧化物层12较厚而提高了保持性能，但由于在数据写/读操作中在隧穿氧化物层12中由施加的电压所自然产生的俘获位置，数据编程和擦除性质变差。
发明内容
本发明提供了一种具有提高的数据保持性质和数据编程/擦除速度的存储器件及其制造方法。
根据本发明的一个方面，提供了一种具有富硅氧化物层的存储器件，所述存储器件具有半导体衬底、形成在所述半导体衬底上的源极/漏极区、和形成在所述半导体衬底上的栅结构，所述栅结构与所述源极/漏极区接触，其中所述栅结构包括具有大于二氧化硅层(SiO2)的硅组分的氧化硅层。
所述栅结构可以包括隧穿氧化物层、浮置栅极和控制栅极。
所述浮置栅极可以由SiOx(1.0＜x＜1.6)形成。
所述隧穿氧化物层可以由SiO2形成。
根据本发明的另一方面，提供了一种制造具有富硅氧化硅层的存储器件的制造方法，所述方法包括：在半导体衬底上形成栅结构，所述栅结构包括具有大于SiO2的硅组分的浮置栅极；蚀刻所述栅结构的两侧以暴露所述半导体衬底的两表面；和在所述暴露的半导体衬底两表面上通过掺杂形成源极和漏极。
所述形成栅结构可以包括：在所述半导体衬底上形成隧穿氧化物层；和在所述隧穿氧化物层上注入硅烷气体(SiH4)和氧气(O2)，以形成具有氧化硅层的浮置栅极，其硅组分高于SiO2的硅组分。
所述硅烷气体(SiH4)和氧气(O2)的流量比可以从1.43∶1到1.57∶1变化。
附图说明
通过参照附图对本发明的示范性实施例的详细描述中，本发明的上述和其他特点和优点将变得更为明显，在附图中：
图1是常规闪存的平面图；
图2是根据本发明实施例的具有富硅氧化硅层的存储器件的平面图；
图3A到3F是示出根据本发明实施例制造具有富硅氧化硅层的存储器件的方法的平面图；
图4是在根据本发明实施例形成富硅氧化硅层之后所获得的TEM照片；
图5A是示出具有根据本发明实施例的富硅氧化硅层的MOS电容结构的C-V曲线的曲线图；以及
图5B是示出根据本发明实施例的具有富硅氧化硅层的存储器件在250℃的保持性质的曲线图。
具体实施方式
将参照附图描述根据本发明实施例的具有富硅氧化硅层的存储器件及其制造方法。
图2是根据本发明实施例的具有富硅氧化物层的存储器件的平面图。参照图2，第一掺杂区21a和第二掺杂区21b形成在半导体衬底20上，且栅结构形成在与第一掺杂区21a和第二掺杂区21b接触的半导体衬底20上。所述栅结构包括隧穿氧化物层22、富硅氧化硅层23、和控制栅极24。
存储器件制造工艺中所使用的任何衬底都可以用作所述半导体衬底20。隧穿氧化物层22由SiO2形成。富硅氧化硅层23由SiOx形成，其中x在1.0到1.6范围内。即，富硅氧化硅层23具有比形成在富硅氧化硅层下面的隧穿氧化物层22高的硅组分比例。控制栅极24可以由闪存制造工艺中所采用的任何导电材料形成。
将详细描述根据本发明实施例的具有富硅氧化硅层的存储器件的制造方法。图3A到3F是示出根据本发明实施例的具有富硅氧化硅层的存储器件的制造顺序工序的平面图。
参照图3A，制备半导体衬底20。存储器件的制造工艺中使用的任何衬底都可以用作半导体衬底20。硅衬底广泛用作所述半导体衬底20。
参照图3B，在所述半导体衬底20上涂覆隧穿氧化物层22。该隧穿氧化物层22由二氧化硅形成(SiO2)。隧穿氧化物层22可以形成为3nm以下厚度，该厚度被认为是常规闪存的极限。
参照图3C，在隧穿氧化物层22上涂覆富硅氧化硅层23。优选在反应腔中硅烷气体(SiH4)与氧气(O2)的流量比控制在1.43到1.57范围内，以淀积富硅氧化物层23。例如，以1.0sccm的硅烷流量和0.7sccm的氧流量淀积富硅氧化硅层23。存储器件的常规制造设备可以用于制造根据本发明实施例的具有富硅氧化硅层23的存储器件。原因是富硅氧化硅层23由与隧穿氧化物层22同等的材料形成，且注入进腔中的供给气体的流量比是惟一需要控制的。
参照图3D，在富硅氧化硅层23上形成控制栅极24。控制栅极24可以通过涂覆已经广泛使用的导电材料而形成。
参照图3E，通过蚀刻工艺除去隧穿氧化物层22、富硅氧化硅层23和控制栅极24的两侧，因此暴露半导体衬底20的两侧表面。
参照图3F，半导体衬底20的暴露侧表面掺杂有掺杂剂，并进行热退火以激活掺杂剂。这样，完成存储器件。
图4是在根据本发明实施例的富硅氧化硅层形成后获得的TEM照片。参照图4，由SRSO表示的区域代表具有约4nm厚度的富硅氧化硅层，且由Tox表示的区域代表由SiO2形成的具有约2nm厚度的隧穿氧化物层22。如果形成硅点，仅SRSO区的一部分将区别显示，但图4的SRSO区由单层均匀地形成为整体。
图5A和5B是示出根据本发明实施例的具有富硅氧化硅层的存储器件的存储性质的曲线图。
图5A所示的图代表关于施加电压的电容性质。当电压变化时，窗口区形成在以-4V为中心的两侧。因此，电荷俘获位置形成在富硅氧化硅层23内。
图5B是示出当将电荷在10V和-10V下注入到具有富硅氧化硅层的电容器结构然后在250℃进行两小时热退火时的平带电压变化的曲线图。公知当在250℃进行两小时热退火时，保持性质在室温下保持十年。参照图5B，当在250℃进行两小时热退火时，保持了约4V的平带电压差，因此提高了保持性质。
根据本发明，浮置栅极由具有比典型的氧化硅层(SiO2)高的硅组分的氧化硅层形成。因此，浮置栅极作为整体具有均匀的组分，并包括电荷俘获位置。而且，形成在浮置栅极下面的隧穿氧化物层可以形成为3nm以下厚度。所述存储器件可以具有好的保持性质。此外，由于所述存储器件采用现有设备制造，制造工艺可以简化。此外，不需要用于硅点的耗时的高温热退火。
虽然参照其示范性实施例具体示出并描述了本发明，但本领域的技术人员应该理解，在不脱离由权利要求所限定的本发明的精神和范畴的情况下，可以对本发明进行各种形式和细节的变化。
Claims (9)
1、一种具有富硅氧化物层的存储器件，所述存储器件具有半导体衬底、形成在所述半导体衬底上的源极/漏极区、和形成在所述半导体衬底上的栅结构，所述栅结构与所述源极/漏极区接触，其中所述栅结构包括具有大于二氧化硅层(SiO2)的硅组分的氧化硅层。
2、如权利要求1所述的存储器件，其中所述栅结构包括隧穿氧化物层、浮置栅极和控制栅极。
3、如权利要求2所述的存储器件，其中所述浮置栅极由SiOx(1.0＜x＜1.6)形成。
4、如权利要求2所述的存储器件，其中所述隧穿氧化物层由SiO2形成。
5、一种制造具有富硅氧化硅层的存储器件的方法，所述方法包括：
在半导体衬底上形成栅结构，所述栅结构包括具有大于SiO2的硅组分的浮置栅极；
蚀刻所述栅结构的两侧以暴露所述半导体衬底的两表面；和
在所述暴露的半导体衬底两表面上通过掺杂形成源极和漏极。
6、如权利要求5所述的方法，其中所述形成栅结构包括：
在所述半导体衬底上形成隧穿氧化物层；和
在所述隧穿氧化物层上注入硅烷气体(SiH4)和氧气(O2)，以形成具有氧化硅层的浮置栅极，其硅组分高于SiO2的硅组分。
7、如权利要求6所述的方法，其中所述硅烷气体(SiH4)和氧气(O2)的流量比从1.43∶1到1.57∶1变化。
8、如权利要求7所述的方法，其中所述浮置栅极由SiOx(1.0＜x＜1.6)形成。
9、如权利要求5所述的方法，其中所述栅结构包括隧穿氧化物层、浮置栅极和控制栅极。
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| KR1020050011733A KR100695140B1 (ko) | 2005-02-12 | 2005-02-12 | 실리콘 리치 산화막을 포함하는 메모리 소자의 제조 방법 |
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|---|---|
| CN1828945A true CN1828945A (zh) | 2006-09-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA2006100042419A Pending CN1828945A (zh) | 2005-02-12 | 2006-02-13 | 具有富硅氧化硅层的存储器件及其制造方法 |
Country Status (4)
| Country | Link |
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| US (1) | US20060180845A1 (zh) |
| JP (1) | JP2006222434A (zh) |
| KR (1) | KR100695140B1 (zh) |
| CN (1) | CN1828945A (zh) |
Families Citing this family (3)
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|---|---|---|---|---|
| JP2007043147A (ja) * | 2005-07-29 | 2007-02-15 | Samsung Electronics Co Ltd | 原子層蒸着工程を用いたシリコンリッチナノクリスタル構造物の形成方法及びこれを用いた不揮発性半導体装置の製造方法 |
| JP2008182035A (ja) * | 2007-01-24 | 2008-08-07 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
| US9794141B2 (en) | 2013-03-14 | 2017-10-17 | Arista Networks, Inc. | System and method for determining a cause of network congestion |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58219748A (ja) * | 1982-06-15 | 1983-12-21 | Toshiba Corp | 半導体装置 |
| US5557122A (en) * | 1995-05-12 | 1996-09-17 | Alliance Semiconductors Corporation | Semiconductor electrode having improved grain structure and oxide growth properties |
| US5837585A (en) * | 1996-07-23 | 1998-11-17 | Vanguard International Semiconductor Corporation | Method of fabricating flash memory cell |
| JP2001085545A (ja) * | 1999-09-16 | 2001-03-30 | Sony Corp | メモリ素子の製造方法 |
| JP2002184873A (ja) * | 2000-10-03 | 2002-06-28 | Sony Corp | 不揮発性半導体記憶装置及びその製造方法 |
| JP5068402B2 (ja) * | 2000-12-28 | 2012-11-07 | 公益財団法人国際科学振興財団 | 誘電体膜およびその形成方法、半導体装置、不揮発性半導体メモリ装置、および半導体装置の製造方法 |
| TW594939B (en) * | 2003-06-26 | 2004-06-21 | Nanya Technology Corp | Read-only memory cell and a production method thereof |
| DE10340202A1 (de) * | 2003-08-28 | 2005-04-14 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Herstellungsverfahren für ein Halbleiterbauelement mit Praseodymoxid-Dielektrikum |
| US7176105B2 (en) * | 2004-06-01 | 2007-02-13 | Applied Materials, Inc. | Dielectric gap fill with oxide selectively deposited over silicon liner |
| JP4928773B2 (ja) * | 2004-12-10 | 2012-05-09 | 株式会社東芝 | 半導体装置 |
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2005
- 2005-02-12 KR KR1020050011733A patent/KR100695140B1/ko not_active IP Right Cessation
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2006
- 2006-02-10 US US11/350,867 patent/US20060180845A1/en not_active Abandoned
- 2006-02-13 CN CNA2006100042419A patent/CN1828945A/zh active Pending
- 2006-02-13 JP JP2006035850A patent/JP2006222434A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR100695140B1 (ko) | 2007-03-14 |
| US20060180845A1 (en) | 2006-08-17 |
| JP2006222434A (ja) | 2006-08-24 |
| KR20060091020A (ko) | 2006-08-17 |
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