CN100477131C - 形成半导体装置的方法 - Google Patents

形成半导体装置的方法 Download PDF

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CN100477131C
CN100477131C CNB2006100938065A CN200610093806A CN100477131C CN 100477131 C CN100477131 C CN 100477131C CN B2006100938065 A CNB2006100938065 A CN B2006100938065A CN 200610093806 A CN200610093806 A CN 200610093806A CN 100477131 C CN100477131 C CN 100477131C
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CN101022084A (zh
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陈豪育
郑水明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种形成半导体装置的方法，包括以下步骤：在一基板上形成一栅极；在该栅极对应侧的基板内形成多个凹口；在该基板的所述凹口内形成一扩散阻障层；在所述凹口内通过外延生长形成一硅层；以及在该硅层上沉积一半导体合金以形成源极/漏极区。本发明提供了具有设置在源极/漏极区内的半导体合金，并可降低或避免掺杂物质扩散进入沟道区的情况发生。

Description

形成半导体装置的方法
技术领域
本发明总的涉及半导体装置，特别是关于金属氧化物半导体晶体管及其制造方法。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)的尺寸缩减包括了栅极长度与栅极氧化物厚度的减少，因而改善了过去数十年来单一功能集成电路装置的速度、性能、密度与成本。为了进一步增进晶体管的性能，MOSFET装置的制作已在部分半导体基板内采用了应变沟道区(strained channelregions)。应变沟道区改善了载流子移动率，进而改善了n沟道装置(NMOS)或p沟道装置(PMOS)的性能。一般对于NMOS晶体管而言，最好在其源极至漏极的方向产生拉伸应变(tensile strain)以增加电子迁移率(electronmobility)，而对于PMOS晶体管而言，则最好在其源极至漏极方向产生压缩应变(compressive strain)以增加空穴迁移率(hole mobility)。目前已有数种在晶体管沟道区处诱发应变的方法。
其中方法之一为通过在源极/漏极区(source/drain regions)中形成例如硅锗(silicon-germanium)或硅锗碳(silicon-germanium-carbon)的半导体合金膜层，该半导体合金膜层具有异于基板的晶格常数。如此不同的晶格常数结构在沟道区中产生了应变，因而增加载流子迁移率。
上述半导体合金层通常为经临场掺杂(in-situ doped)的磊晶层，其具有低电阻值且诱发了沟道区内应变。然而，其所掺杂的掺杂物质在磊晶热过程时将有可能扩散至沟道区中，进而劣化了半导体装置的短沟道效应特性。再者，在PMOS装置中通过采用氢来改善磊晶质量。然而，氢的使用也劣化了负偏压温度稳定度(negative bias temperature instability，NBTI)。
因此，需要一种半导体装置及其制造方法，其具有设置在源极/漏极区内的半导体合金，并可降低或避免掺杂物质扩散进入沟道区的情况发生。
发明内容
有鉴于此，本发明提供了形成半导体装置的方法。
在一实施例中，本发明的形成半导体装置的方法，包括以下步骤：
在一基板上形成一栅极；在该栅极对应侧的基板内形成多个凹口；在该基板的所述凹口内形成一扩散阻障层；在所述凹口内通过外延生长形成一硅层；以及在该硅层上沉积一半导体合金，以形成源极/漏极区。
如本发明所述的形成半导体装置的方法，其中所述凹口具有大于50纳米的深度。
如本发明所述的形成半导体装置的方法，其中所述凹口具有大于10纳米的宽度。
如本发明所述的形成半导体装置的方法，其中该扩散阻障层包括一富氟硅层、一富碳硅层、一富氮硅层或其组合。
如本发明所述的形成半导体装置的方法，其中该富氟硅层具有介于1-10纳米的厚度。
在另一实施例中，本发明的形成半导体装置的方法，包括以下步骤：
在一基板上形成一栅极；凹蚀该基板，以形成邻近该栅极的多个源极/漏极区；在所述源极/漏极区内形成一阻障层；在所述源极/漏极区内通过外延生长形成一硅层；以及在该硅层上形成一半导体合金。
如本发明所述的形成半导体装置的方法，其中该凹蚀该基板包括凹蚀所述源极/漏极区内的基板达到大于50纳米的深度的步骤。
如本发明所述的形成半导体装置的方法，其中该凹蚀该基板包括凹蚀所述源极/漏极区内的基板达到大于10纳米的宽度的步骤。
如本发明所述的形成半导体装置的方法，其中形成该阻障层包括掺杂氟、碳与氮离子在所述凹口的基底内的步骤。
如本发明所述的形成半导体装置的方法，其中该阻障层具有介于1-10纳米的厚度。
在再一实施例中，本发明的形成半导体装置的方法，包括以下步骤：
提供一基板；在该基板上形成一栅极；在该栅极的对应侧形成间隔物；凹蚀邻近所述间隔物的基板，进而形成多个凹口；在所述凹口内形成一阻障层；在所述凹口内通过外延生长形成一硅层；以及在该硅层上形成一第二半导体层，该第二半导体层具有异于该硅层的一晶格常数。
如本发明所述的形成半导体装置的方法，其中形成该阻障层包括掺杂氟、碳与氮离子在所述凹口的基底内的步骤。
如本发明所述的形成半导体装置的方法，其中形成该第二半导体层包括沉积硅锗、硅碳或硅碳锗的步骤。
本发明提供了具有设置在源极/漏极区内的半导体合金，并可降低或避免掺杂物质扩散进入沟道区的情况发生。为了让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举一较佳实施例，并配合所附图示，作详细说明如下：
附图说明
图1-6分别显示了依据本发明之一实施例的具有扩散阻障层的MOSFET在制作中的不同过程步骤情况。
其中，附图标记说明如下：
110  基板；
112  栅极介电层；
114  栅极；
116  掩模层；
118  浅沟槽隔离物；
210  牺牲衬层；
212  牺牲间隔物；
310  凹口；
410  阻障层；
510  第一半导体层；
610  第二半导体层。
具体实施方式
图1-6分别图示了依据本发明之一实施例的具有扩散阻障层的半导体装置的制作情况。在此图标的实施例适用于多种电路的制作。具体的，本发明的实施例特别适用于65纳米以下的晶体管设计，其中的掺杂物质穿透进入基板的情况特别地严重。其所使用的扩散阻障层有助于改善装置的可靠性。
请参照图1，其中显示了依据本发明一实施例在其上的基板110设置栅极介电层112与栅极114。在一实施例中，基板110包括一P型块状硅基底(bulk silicon substrate)。基板110也可采用其它材料，例如是锗、硅锗合金或相似物。基板110也可为一绝缘层上覆硅基板(SOI)或为一多层结构上的一有源层，例如为形成在块状硅层上的一硅锗层。一般而言，绝缘层上覆硅基板包括一半导体层，例如形成一绝缘层上的硅层。上述绝缘层则例如为埋入氧化层(BOX)或二氧化硅层。绝缘层通常是形成于如硅基板或玻璃基板的一基板上。其它基板则例如为一多膜层基板或一梯度基板(gradientsubstrate)。在基板内还可设置有P阱及/或N阱，借以进一步分别隔离NMOS装置与PMOS装置。
栅极介电层112与栅极114可通过在基板110上的沉积与图案化一介电层与一导电层所形成。介电层较佳地包括如二氧化硅、氮氧化硅、氮化硅、含氮的氧化物、高介电常数金属氧化物、上述材料的组成或相似物等介电材料。二氧化硅材料的介电层可通过如湿式或干式热氧化的氧化过程所形成，或通过如低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)或原子层化学气相沉积(ALCVD)等化学气相沉积(CVD)方式所形成。
导电层包括导电材料，例如金属(如钽、钛、钼、钨、铂、铝、铪、炉)、金属硅化物(如硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(如氮化钛、氮化钽)、经掺杂的多晶硅、其它导电材料或上述材料的组合物。在一范例中，可先行沉积一非晶硅并重新结晶而制作出多晶硅。在较佳实施例中，栅极114为多晶硅材料且可通过低压化学气相沉积(LPCVD)形成经掺杂或未经掺杂的多晶硅。接着多晶硅可掺杂N型或P型掺杂物质以分别形成一NMOS装置或一PMOS装置。
栅极介电层112与栅极114可通过已知光刻技术图案化而形成。光刻通常包括沉积抗蚀剂材料，接着掩蔽、曝光并显影此抗蚀剂材料。在抗蚀剂图案化后，可通过施行非等向性蚀刻过程移除不需要的介电层与导电层部分，而分别形成如图1所示的栅极介电层112与栅极114。
在栅极114上可进一步选择地形成一掩模层116，以保护下方的栅极材料免于在蚀刻过程中被移除。适当的掩模层116包括氧化物层与氮化物层。在一实施例中，氧化物层包括氮氧化硅而氮化物层包括氮化硅。其也可采用其它材料。
在基板110内可形成有浅沟槽隔离物118或如场氧化物区的其它隔离结构，以隔离基板上的有源区。浅沟槽隔离物118可通过蚀刻基板110在其内形成沟槽，并在沟槽中填入如二氧化硅、高密度等离子体氧化物或相似物的介电材料。
图2则图示了基板110在邻近在栅极114的侧壁上形成有牺牲衬层210与牺牲间隔物212的情况。牺牲衬层210较佳地为一氧化物层，其通过如采用四乙氧基硅烷(TEOS)与氧气作为反应物的化学气相沉积技术而形成。牺牲间隔物212较佳地包括氮化硅(Si3N4)或其它含氮膜层，例如氮化硅(SixNy)、氮氧化硅、硅的含氮化合物(silicon oxime)或上述材料的组合。在一较佳实施例中，牺牲间隔物212采用利用硅甲烷与氨气为反应物化学气相沉积形成的氮化硅(Si3N4)的膜层，其沉积温度约介于400-600℃。在一实施例中，牺牲衬层210与牺牲间隔物212的结合厚度大于约30埃。
值得注意的，牺牲衬层210与牺牲间隔物212可能包括不同材料。然而，用于牺牲衬层210与牺牲间隔物212的材料间需具有选择性，从而使得牺牲衬层210与牺牲间隔物212的材料间具有高蚀刻选择比。
图3图示了依据本发明之一实施例中，在基底110内形成数个凹口310后的情况。所述凹口310可通过非等向性或等向性的蚀刻过程而形成，其较佳地通过非等向性蚀刻而形成，且较佳地为一干蚀刻过程。在一实施例中，凹口的深度大于约50纳米。如图3所示，所述凹口310较佳地横向延伸至部分的牺牲间隔物212的下方约大于10纳米的一距离。
图4图示了依据本发明一实施例中当图3所示的基板110在沿着凹口310表面形成有阻障层410的情况。在一实施例中，阻障层410通过注入如氟离子的离子而形成。可发现通过注入氟离子在凹口310表面后，在形成应变诱发层(在下文中讨论并参照图6)时可避免或减少氢原子的穿透情况，进而改善了晶体管的NBTI特性。再者，氟离子也有助于抑制掺杂物质扩散进入源极/漏极区，因而可降低短沟道区的漏极引起阻障降低(DIBL)劣化的情况。在一实施例中，上述注入过程包括在剂量介于1E13～1E15原子/每平方厘米与能量介于0.3～2KeV的条件下注入氟离子。此外，也可采用如碳、氮或其组合或相似物等的其它离子以及如离子等离子体注入、气体回火、低压注入或相似的其它过程。在此，阻障层114的厚度较佳地介于1～10纳米。
图5图示了依据本发明之一实施例中，在图4中所示的基板110在沿着凹口310选择性地形成第一半导体层510后的情况。在一实施例中，第一半导体层510由相似于基底110的半导体材料所形成，例如为硅材料。如下文中的描述，凹口310较佳地为一应变诱发层所填入，且可发现到形成于阻障层410上的硅层在后续步骤中当应变诱发层形成时，可通过避免或降低阻障层410的扩散进入应变诱发层因而有助于避免应变的松弛。
如此，当基板110由硅材料所制成时，第一半导体层510可为利用基板110作为籽晶层而选择性形成的磊晶层。第一半导体510的厚度较佳地约为1-10纳米。
或者，在形成第一半导体层510之前还可施行一回火过程(例如为快速热回火(RTA)或炉管热回火)。在一实施例中，可在约700-1020℃的温度下通过施行快速热回火约0秒至1分钟来修复凹口310内的基板110表面，进而制造出用于形成第一半导体层510的一平滑表面。由于形成在如此的平滑表面上，第一半导体层510可较为均匀并具有较少的缺陷。
图6则图示了依据本发明之一实施例中，当图5中基板110在源极/漏极区形成有一第二半导体层610的情况。较佳地，第二半导体层610为用于诱发在晶体管沟道区处应变的一应变诱发层，借以改善晶体管的性能。如已知所述，经应变的沟道区有助于改善载流子迁移率，且进而改善了PMOS与NMOS装置的性能。通常，对于NMOS晶体管而言，较佳地在其源极至漏极的方向产生拉伸应变(tensile strain)以增加电子迁移率(electron mobility)，而对于PMOS晶体管而言，则较佳地在其源极至漏极方向产生压缩应变(compressive strain)以增加空穴迁移率(hole mobility)。
如此，对PMOS装置而言，第二半导体层610可为一硅锗合金层。较佳地，该硅锗合金层通过如超高压化学气相沉积或分子束磊晶而通过外延生长形成的一大体单晶层。对于一NMOS装置而言，第二半导体层610可为通过外延生长形成的硅碳或硅锗碳膜层。其也可使用其它材料。
第二半导体层610的厚度较佳地具有介于400-900埃且可高出于基板110的表面，例如高出源极/漏极的表面。
如此，接着可采用标准制造技术以完成PMOS或NMOS晶体管的制作。举例来说，可接着移除牺牲衬层210与牺牲间隔物212，并通过掺杂N型或P型离子而形成源极/漏极区，并接着金属硅化接触区域进行后续过程。
虽然本发明已以较佳实施例公开如上，但其并非用以限定本发明，任何本领域的技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视后附的权利要求书所界定的为准。

Claims (13)

1.一种形成半导体装置的方法，包括下列步骤：
在一基板上形成一栅极；
在该栅极对应侧的基板内形成多个凹口；
在该基板的所述凹口内形成一扩散阻障层；
在所述凹口内通过外延生长形成一硅层；以及
在该硅层上沉积一半导体合金，以形成源极/漏极区。
2.如权利要求1所述的形成半导体装置的方法，其特征在于所述凹口具有大于50纳米的深度。
3.如权利要求1所述的形成半导体装置的方法，其特征在于所述凹口具有大于10纳米的宽度。
4.如权利要求1所述的形成半导体装置的方法，其特征在于该扩散阻障层包括一富氟硅层、一富碳硅层、一富氮硅层或其组合。
5.如权利要求4所述的形成半导体装置的方法，其特征在于该富氟硅层具有介于1-10纳米的厚度。
6.一种形成半导体装置的方法，包括下列步骤：
在一基板上形成一栅极；
凹蚀该基板，以形成邻近该栅极的多个源极/漏极区；
在所述源极/漏极区内形成一阻障层；
在所述源极/漏极区内通过外延生长形成一硅层；以及
在该硅层上形成一半导体合金。
7.如权利要求6所述的形成半导体装置的方法，其特征在于该凹蚀该基板包括凹蚀所述源极/漏极区内的基板达到大于50纳米的深度的步骤。
8.如权利要求6所述的形成半导体装置的方法，其特征在于该凹蚀该基板包括凹蚀所述源极/漏极区内的基板达到大于10纳米的宽度的步骤。
9.如权利要求6所述的形成半导体装置的方法，其特征在于形成该阻障层包括掺杂氟、碳与氮离子在所述凹口的基底内的步骤。
10.如权利要求6所述的形成半导体装置的方法，其特征在于该阻障层具有介于1-10纳米的厚度。
11.一种形成半导体装置的方法，包括下列步骤：
提供一基板；
在该基板上形成一栅极；
在该栅极的对应侧形成间隔物；
凹蚀邻近所述间隔物的基板，进而形成多个凹口；
在所述凹口内形成一阻障层；
在所述凹口内通过外延生长形成一硅层；以及
在该硅层上形成一第二半导体层，该第二半导体层具有异于该硅层的一晶格常数。
12.如权利要求11所述的形成半导体装置的方法，其特征在于形成该阻障层包括掺杂氟、碳与氮离子在所述凹口的基底内的步骤。
13.如权利要求11所述的形成半导体装置的方法，其特征在于形成该第二半导体层包括沉积硅锗、硅碳或硅碳锗的步骤。
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